forked from Minki/linux
ioat3: xor support
ioat3.2 adds xor offload support for up to 8 sources. It can also perform an xor-zero-sum operation to validate whether all given sources sum to zero, without writing to a destination. Xor descriptors differ from memcpy in that one operation may require multiple descriptors depending on the number of sources. When the number of sources exceeds 5 an extended descriptor is needed. These descriptors need to be accounted for when updating the DMA_COUNT register. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
e61dacaeb3
commit
b094ad3be5
@ -48,7 +48,7 @@ module_param(ioat_ring_max_alloc_order, int, 0644);
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MODULE_PARM_DESC(ioat_ring_max_alloc_order,
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"ioat2+: upper limit for dynamic ring resizing (default: n=16)");
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static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
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void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
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{
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void * __iomem reg_base = ioat->base.reg_base;
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@ -127,6 +127,7 @@ static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len
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* @raw: hardware raw (un-typed) descriptor
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* @txd: the generic software descriptor for all engines
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* @len: total transaction length for unmap
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* @result: asynchronous result of validate operations
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* @id: identifier for debug
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*/
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@ -143,6 +144,7 @@ struct ioat_ring_ent {
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};
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struct dma_async_tx_descriptor txd;
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size_t len;
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enum sum_check_flags *result;
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#ifdef DEBUG
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int id;
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#endif
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@ -180,5 +182,6 @@ enum dma_status ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie,
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dma_cookie_t *done, dma_cookie_t *used);
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void __ioat2_restart_chan(struct ioat2_dma_chan *ioat);
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bool reshape_ring(struct ioat2_dma_chan *ioat, int order);
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void __ioat2_issue_pending(struct ioat2_dma_chan *ioat);
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extern struct kobj_type ioat2_ktype;
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#endif /* IOATDMA_V2_H */
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@ -64,8 +64,33 @@
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#include "dma.h"
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#include "dma_v2.h"
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/* ioat hardware assumes at least two sources for raid operations */
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#define src_cnt_to_sw(x) ((x) + 2)
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#define src_cnt_to_hw(x) ((x) - 2)
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/* provide a lookup table for setting the source address in the base or
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* extended descriptor of an xor descriptor
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*/
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static const u8 xor_idx_to_desc __read_mostly = 0xd0;
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static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 };
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static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx)
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{
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struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
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return raw->field[xor_idx_to_field[idx]];
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}
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static void xor_set_src(struct ioat_raw_descriptor *descs[2],
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dma_addr_t addr, u32 offset, int idx)
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{
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struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
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raw->field[xor_idx_to_field[idx]] = addr + offset;
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}
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static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
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struct ioat_ring_ent *desc)
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struct ioat_ring_ent *desc, int idx)
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{
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struct ioat_chan_common *chan = &ioat->base;
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struct pci_dev *pdev = chan->device->pdev;
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@ -86,13 +111,71 @@ static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
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PCI_DMA_FROMDEVICE, flags, 1);
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break;
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}
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case IOAT_OP_XOR_VAL:
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case IOAT_OP_XOR: {
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struct ioat_xor_descriptor *xor = desc->xor;
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struct ioat_ring_ent *ext;
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struct ioat_xor_ext_descriptor *xor_ex = NULL;
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int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt);
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struct ioat_raw_descriptor *descs[2];
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int i;
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if (src_cnt > 5) {
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ext = ioat2_get_ring_ent(ioat, idx + 1);
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xor_ex = ext->xor_ex;
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}
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if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
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descs[0] = (struct ioat_raw_descriptor *) xor;
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descs[1] = (struct ioat_raw_descriptor *) xor_ex;
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for (i = 0; i < src_cnt; i++) {
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dma_addr_t src = xor_get_src(descs, i);
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ioat_unmap(pdev, src - offset, len,
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PCI_DMA_TODEVICE, flags, 0);
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}
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/* dest is a source in xor validate operations */
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if (xor->ctl_f.op == IOAT_OP_XOR_VAL) {
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ioat_unmap(pdev, xor->dst_addr - offset, len,
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PCI_DMA_TODEVICE, flags, 1);
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break;
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}
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}
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if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
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ioat_unmap(pdev, xor->dst_addr - offset, len,
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PCI_DMA_FROMDEVICE, flags, 1);
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break;
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}
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default:
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dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
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__func__, desc->hw->ctl_f.op);
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}
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}
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static bool desc_has_ext(struct ioat_ring_ent *desc)
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{
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struct ioat_dma_descriptor *hw = desc->hw;
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if (hw->ctl_f.op == IOAT_OP_XOR ||
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hw->ctl_f.op == IOAT_OP_XOR_VAL) {
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struct ioat_xor_descriptor *xor = desc->xor;
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if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
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return true;
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}
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return false;
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}
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/**
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* __cleanup - reclaim used descriptors
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* @ioat: channel (ring) to clean
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*
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* The difference from the dma_v2.c __cleanup() is that this routine
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* handles extended descriptors and dma-unmapping raid operations.
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*/
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static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
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{
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struct ioat_chan_common *chan = &ioat->base;
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@ -114,7 +197,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
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tx = &desc->txd;
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if (tx->cookie) {
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chan->completed_cookie = tx->cookie;
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ioat3_dma_unmap(ioat, desc);
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ioat3_dma_unmap(ioat, desc, ioat->tail + i);
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tx->cookie = 0;
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if (tx->callback) {
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tx->callback(tx->callback_param);
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@ -124,6 +207,12 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
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if (tx->phys == phys_complete)
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seen_current = true;
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/* skip extended descriptors */
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if (desc_has_ext(desc)) {
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BUG_ON(i + 1 >= active);
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i++;
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}
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}
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ioat->tail += i;
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BUG_ON(!seen_current); /* no active descs have written a completion? */
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@ -309,6 +398,121 @@ ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value,
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return &desc->txd;
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}
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static struct dma_async_tx_descriptor *
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__ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,
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dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt,
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size_t len, unsigned long flags)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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struct ioat_ring_ent *compl_desc;
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struct ioat_ring_ent *desc;
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struct ioat_ring_ent *ext;
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size_t total_len = len;
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struct ioat_xor_descriptor *xor;
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struct ioat_xor_ext_descriptor *xor_ex = NULL;
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struct ioat_dma_descriptor *hw;
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u32 offset = 0;
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int num_descs;
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int with_ext;
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int i;
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u16 idx;
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u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR;
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BUG_ON(src_cnt < 2);
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num_descs = ioat2_xferlen_to_descs(ioat, len);
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/* we need 2x the number of descriptors to cover greater than 5
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* sources
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*/
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if (src_cnt > 5) {
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with_ext = 1;
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num_descs *= 2;
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} else
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with_ext = 0;
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/* completion writes from the raid engine may pass completion
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* writes from the legacy engine, so we need one extra null
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* (legacy) descriptor to ensure all completion writes arrive in
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* order.
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*/
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if (likely(num_descs) &&
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ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0)
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/* pass */;
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else
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return NULL;
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for (i = 0; i < num_descs; i += 1 + with_ext) {
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struct ioat_raw_descriptor *descs[2];
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size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
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int s;
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desc = ioat2_get_ring_ent(ioat, idx + i);
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xor = desc->xor;
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/* save a branch by unconditionally retrieving the
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* extended descriptor xor_set_src() knows to not write
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* to it in the single descriptor case
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*/
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ext = ioat2_get_ring_ent(ioat, idx + i + 1);
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xor_ex = ext->xor_ex;
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descs[0] = (struct ioat_raw_descriptor *) xor;
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descs[1] = (struct ioat_raw_descriptor *) xor_ex;
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for (s = 0; s < src_cnt; s++)
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xor_set_src(descs, src[s], offset, s);
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xor->size = xfer_size;
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xor->dst_addr = dest + offset;
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xor->ctl = 0;
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xor->ctl_f.op = op;
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xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt);
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len -= xfer_size;
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offset += xfer_size;
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dump_desc_dbg(ioat, desc);
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}
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/* last xor descriptor carries the unmap parameters and fence bit */
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desc->txd.flags = flags;
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desc->len = total_len;
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if (result)
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desc->result = result;
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xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
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/* completion descriptor carries interrupt bit */
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compl_desc = ioat2_get_ring_ent(ioat, idx + i);
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compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
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hw = compl_desc->hw;
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hw->ctl = 0;
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hw->ctl_f.null = 1;
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
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hw->ctl_f.compl_write = 1;
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hw->size = NULL_DESC_BUFFER_SIZE;
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dump_desc_dbg(ioat, compl_desc);
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/* we leave the channel locked to ensure in order submission */
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return &desc->txd;
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}
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static struct dma_async_tx_descriptor *
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ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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unsigned int src_cnt, size_t len, unsigned long flags)
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{
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return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
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}
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struct dma_async_tx_descriptor *
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ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
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unsigned int src_cnt, size_t len,
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enum sum_check_flags *result, unsigned long flags)
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{
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/* the cleanup routine only sets bits on validate failure, it
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* does not clear bits on validate success... so clear it here
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*/
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*result = 0;
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return __ioat3_prep_xor_lock(chan, result, src[0], &src[1],
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src_cnt - 1, len, flags);
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}
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int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
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{
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struct pci_dev *pdev = device->pdev;
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@ -333,6 +537,16 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
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dma_cap_set(DMA_MEMSET, dma->cap_mask);
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dma->device_prep_dma_memset = ioat3_prep_memset_lock;
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}
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if (cap & IOAT_CAP_XOR) {
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dma->max_xor = 8;
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dma->xor_align = 2;
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dma_cap_set(DMA_XOR, dma->cap_mask);
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dma->device_prep_dma_xor = ioat3_prep_xor;
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dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
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dma->device_prep_dma_xor_val = ioat3_prep_xor_val;
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}
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/* -= IOAT ver.3 workarounds =- */
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/* Write CHANERRMSK_INT with 3E07h to mask out the errors
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@ -243,6 +243,8 @@
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#define IOAT_CHANERR_XOR_Q_ERR 0x20000
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#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000
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#define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)
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#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
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#endif /* _IOAT_REGISTERS_H_ */
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