staging: ccree: copy larval digest from RAM
The ccree driver was using a DMA operation to copy larval digest from the ccree SRAM to RAM. Replace it with a simple memcpy. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef
Greg Kroah-Hartman
parent
1b33fb7aed
commit
b070ed04c3
@ -484,6 +484,8 @@ static int __init ccree_init(void)
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{
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int ret;
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cc_hash_global_init();
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ret = cc_debugfs_global_init();
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if (ret)
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return ret;
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@ -41,10 +41,10 @@ static const u32 sha256_init[] = {
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#if (CC_DEV_SHA_MAX > 256)
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static const u32 digest_len_sha512_init[] = {
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0x00000080, 0x00000000, 0x00000000, 0x00000000 };
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static const u64 sha384_init[] = {
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static u64 sha384_init[] = {
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SHA384_H7, SHA384_H6, SHA384_H5, SHA384_H4,
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SHA384_H3, SHA384_H2, SHA384_H1, SHA384_H0 };
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static const u64 sha512_init[] = {
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static u64 sha512_init[] = {
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SHA512_H7, SHA512_H6, SHA512_H5, SHA512_H4,
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SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 };
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#endif
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@ -55,6 +55,8 @@ static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[],
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static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[],
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unsigned int *seq_size);
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static const void *cc_larval_digest(struct device *dev, u32 mode);
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struct cc_hash_alg {
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struct list_head entry;
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int hash_mode;
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@ -126,10 +128,6 @@ static int cc_map_req(struct device *dev, struct ahash_req_ctx *state,
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struct cc_hash_ctx *ctx, gfp_t flags)
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{
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bool is_hmac = ctx->is_hmac;
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cc_sram_addr_t larval_digest_addr =
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cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode);
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struct cc_crypto_req cc_req = {};
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struct cc_hw_desc desc;
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int rc = -ENOMEM;
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state->buff0 = kzalloc(CC_MAX_HASH_BLCK_SIZE, flags);
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@ -203,9 +201,6 @@ static int cc_map_req(struct device *dev, struct ahash_req_ctx *state,
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HASH_LEN_SIZE);
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#endif
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}
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dma_sync_single_for_device(dev, state->digest_buff_dma_addr,
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ctx->inter_digestsize,
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DMA_BIDIRECTIONAL);
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if (ctx->hash_mode != DRV_HASH_NULL) {
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dma_sync_single_for_cpu(dev,
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@ -216,22 +211,15 @@ static int cc_map_req(struct device *dev, struct ahash_req_ctx *state,
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ctx->opad_tmp_keys_buff, ctx->inter_digestsize);
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}
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} else { /*hash*/
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/* Copy the initial digests if hash flow. The SRAM contains the
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* initial digests in the expected order for all SHA*
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*/
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hw_desc_init(&desc);
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set_din_sram(&desc, larval_digest_addr, ctx->inter_digestsize);
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set_dout_dlli(&desc, state->digest_buff_dma_addr,
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ctx->inter_digestsize, NS_BIT, 0);
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set_flow_mode(&desc, BYPASS);
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/* Copy the initial digests if hash flow. */
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const void *larval = cc_larval_digest(dev, ctx->hash_mode);
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rc = send_request(ctx->drvdata, &cc_req, &desc, 1, 0);
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if (rc) {
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dev_err(dev, "send_request() failed (rc=%d)\n", rc);
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goto fail4;
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}
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memcpy(state->digest_buff, larval, ctx->inter_digestsize);
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}
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dma_sync_single_for_device(dev, state->digest_buff_dma_addr,
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ctx->inter_digestsize, DMA_BIDIRECTIONAL);
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if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) {
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state->digest_bytes_len_dma_addr =
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dma_map_single(dev, (void *)state->digest_bytes_len,
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@ -2003,11 +1991,7 @@ int cc_init_hash_sram(struct cc_drvdata *drvdata)
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cc_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr;
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unsigned int larval_seq_len = 0;
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struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)];
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struct device *dev = drvdata_to_dev(drvdata);
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int rc = 0;
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#if (CC_DEV_SHA_MAX > 256)
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int i;
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#endif
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/* Copy-to-sram digest-len */
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cc_set_sram_desc(digest_len_init, sram_buff_ofs,
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@ -2074,49 +2058,49 @@ int cc_init_hash_sram(struct cc_drvdata *drvdata)
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larval_seq_len = 0;
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#if (CC_DEV_SHA_MAX > 256)
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/* We are forced to swap each double-word larval before copying to
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* sram
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*/
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for (i = 0; i < ARRAY_SIZE(sha384_init); i++) {
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const u32 const0 = ((u32 *)((u64 *)&sha384_init[i]))[1];
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const u32 const1 = ((u32 *)((u64 *)&sha384_init[i]))[0];
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cc_set_sram_desc(&const0, sram_buff_ofs, 1, larval_seq,
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&larval_seq_len);
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sram_buff_ofs += sizeof(u32);
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cc_set_sram_desc(&const1, sram_buff_ofs, 1, larval_seq,
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&larval_seq_len);
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sram_buff_ofs += sizeof(u32);
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}
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cc_set_sram_desc((u32 *)sha384_init, sram_buff_ofs,
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(ARRAY_SIZE(sha384_init) * 2), larval_seq,
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&larval_seq_len);
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rc = send_request_init(drvdata, larval_seq, larval_seq_len);
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if (rc) {
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dev_err(dev, "send_request() failed (rc = %d)\n", rc);
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if (rc)
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goto init_digest_const_err;
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}
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sram_buff_ofs += sizeof(sha384_init);
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larval_seq_len = 0;
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for (i = 0; i < ARRAY_SIZE(sha512_init); i++) {
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const u32 const0 = ((u32 *)((u64 *)&sha512_init[i]))[1];
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const u32 const1 = ((u32 *)((u64 *)&sha512_init[i]))[0];
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cc_set_sram_desc(&const0, sram_buff_ofs, 1, larval_seq,
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&larval_seq_len);
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sram_buff_ofs += sizeof(u32);
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cc_set_sram_desc(&const1, sram_buff_ofs, 1, larval_seq,
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&larval_seq_len);
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sram_buff_ofs += sizeof(u32);
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}
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cc_set_sram_desc((u32 *)sha512_init, sram_buff_ofs,
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(ARRAY_SIZE(sha512_init) * 2), larval_seq,
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&larval_seq_len);
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rc = send_request_init(drvdata, larval_seq, larval_seq_len);
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if (rc) {
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dev_err(dev, "send_request() failed (rc = %d)\n", rc);
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if (rc)
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goto init_digest_const_err;
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}
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#endif
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init_digest_const_err:
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return rc;
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}
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static void __init cc_swap_dwords(u32 *buf, unsigned long size)
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{
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int i;
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u32 tmp;
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for (i = 0; i < size; i += 2) {
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tmp = buf[i];
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buf[i] = buf[i + 1];
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buf[i + 1] = tmp;
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}
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}
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/*
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* Due to the way the HW works we need to swap every
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* double word in the SHA384 and SHA512 larval hashes
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*/
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void __init cc_hash_global_init(void)
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{
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cc_swap_dwords((u32 *)&sha384_init, (ARRAY_SIZE(sha384_init) * 2));
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cc_swap_dwords((u32 *)&sha512_init, (ARRAY_SIZE(sha512_init) * 2));
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}
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int cc_hash_alloc(struct cc_drvdata *drvdata)
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{
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struct cc_hash_handle *hash_handle;
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@ -2373,6 +2357,29 @@ static void cc_set_desc(struct ahash_req_ctx *areq_ctx,
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*seq_size = idx;
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}
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static const void *cc_larval_digest(struct device *dev, u32 mode)
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{
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switch (mode) {
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case DRV_HASH_MD5:
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return md5_init;
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case DRV_HASH_SHA1:
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return sha1_init;
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case DRV_HASH_SHA224:
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return sha224_init;
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case DRV_HASH_SHA256:
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return sha256_init;
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#if (CC_DEV_SHA_MAX > 256)
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case DRV_HASH_SHA384:
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return sha384_init;
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case DRV_HASH_SHA512:
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return sha512_init;
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#endif
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default:
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dev_err(dev, "Invalid hash mode (%d)\n", mode);
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return md5_init;
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}
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}
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/*!
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* Gets the address of the initial digest in SRAM
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* according to the given hash mode
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@ -90,5 +90,7 @@ cc_digest_len_addr(void *drvdata, u32 mode);
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*/
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cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode);
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void cc_hash_global_init(void);
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#endif /*__CC_HASH_H__*/
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