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drm/amd/powerplay: move SMUM_WAIT_INDIRECT_FIELD_UNEQUAL to hwmgr.h

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the macro is not relevent to SMU, so move to hwmgr.h
and rename to PHM_WAIT_INDIRECT_FIELD_UNEQUAL

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2017-09-20 19:28:29 +08:00 committed by Alex Deucher
parent d92cb1629b
commit b05720cbf6
4 changed files with 16 additions and 12 deletions
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13
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
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@ -889,4 +889,17 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_t
PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
phm_wait_for_indirect_register_unequal(hwmgr, \
mm##port##_INDEX, index, value, mask)
#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
(fieldval) << PHM_FIELD_SHIFT(reg, field), \
PHM_FIELD_MASK(reg, field) )
#endif /* _HWMGR_H_ */ #endif /* _HWMGR_H_ */

11
drivers/gpu/drm/amd/powerplay/inc/smumgr.h
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@ -117,6 +117,7 @@ extern void smum_wait_for_indirect_register_unequal(
uint32_t indirect_port, uint32_t index, uint32_t indirect_port, uint32_t index,
uint32_t value, uint32_t mask); uint32_t value, uint32_t mask);
extern int smu_allocate_memory(void *device, uint32_t size, extern int smu_allocate_memory(void *device, uint32_t size,
enum cgs_gpu_mem_type type, enum cgs_gpu_mem_type type,
uint32_t byte_align, uint64_t *mc_addr, uint32_t byte_align, uint64_t *mc_addr,
@ -242,15 +243,5 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \ (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field)) SMUM_FIELD_MASK(reg, field))
#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
smum_wait_for_indirect_register_unequal(hwmgr, \
mm##port##_INDEX, index, value, mask)
#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field) )
#endif #endif

2
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
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@ -63,7 +63,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
int result = 0; int result = 0;
/* Wait for smc boot up */ /* Wait for smc boot up */
/* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); */ RCU_UC_EVENTS, boot_seq_done, 0); */
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,

2
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
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@ -137,7 +137,7 @@ static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
} }
/* wait for smc boot up */ /* wait for smc boot up */
SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); RCU_UC_EVENTS, boot_seq_done, 0);
/* clear firmware interrupt enable flag */ /* clear firmware interrupt enable flag */