iommu/mediatek: Move inv_sel_reg into the plat_data
For mt6779, MMU_INV_SEL register's offset is changed from 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to use it. In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it before mt6779. Signed-off-by: Chao Hao <chao.hao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Cc: Yong Wu <yong.wu@mediatek.com> Link: https://lore.kernel.org/r/20200703044127.27438-6-chao.hao@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -37,7 +37,7 @@
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#define REG_MMU_INVLD_START_A 0x024
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#define REG_MMU_INVLD_END_A 0x028
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#define REG_MMU_INV_SEL 0x038
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#define REG_MMU_INV_SEL_GEN1 0x038
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#define F_INVLD_EN0 BIT(0)
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#define F_INVLD_EN1 BIT(1)
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@ -178,7 +178,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
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for_each_m4u(data) {
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
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data->base + REG_MMU_INV_SEL);
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data->base + data->plat_data->inv_sel_reg);
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writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
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wmb(); /* Make sure the tlb flush all done */
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}
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@ -195,7 +195,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
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for_each_m4u(data) {
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spin_lock_irqsave(&data->tlb_lock, flags);
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
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data->base + REG_MMU_INV_SEL);
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data->base + data->plat_data->inv_sel_reg);
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writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
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writel_relaxed(iova + size - 1,
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@ -784,18 +784,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
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static const struct mtk_iommu_plat_data mt2712_data = {
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.m4u_plat = M4U_MT2712,
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.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
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};
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static const struct mtk_iommu_plat_data mt8173_data = {
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.m4u_plat = M4U_MT8173,
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.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
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};
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static const struct mtk_iommu_plat_data mt8183_data = {
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.m4u_plat = M4U_MT8183,
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.flags = RESET_AXI,
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.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
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.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
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};
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@ -40,6 +40,7 @@ enum mtk_iommu_plat {
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struct mtk_iommu_plat_data {
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enum mtk_iommu_plat m4u_plat;
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u32 flags;
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u32 inv_sel_reg;
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unsigned char larbid_remap[MTK_LARB_NR_MAX];
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};
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