forked from Minki/linux
perf, x86: Change x86_pmu.{enable,disable} calling convention
Pass the full perf_event into the x86_pmu functions so that those may make use of more than the hw_perf_event, and while doing this, remove the superfluous second argument. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: paulus@samba.org Cc: eranian@google.com Cc: robert.richter@amd.com Cc: fweisbec@gmail.com Cc: Arnaldo Carvalho de Melo <acme@infradead.org> LKML-Reference: <20100304140100.165166129@chello.nl> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -133,8 +133,8 @@ struct x86_pmu {
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int (*handle_irq)(struct pt_regs *);
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void (*disable_all)(void);
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void (*enable_all)(void);
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void (*enable)(struct hw_perf_event *, int);
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void (*disable)(struct hw_perf_event *, int);
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void (*enable)(struct perf_event *);
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void (*disable)(struct perf_event *);
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unsigned eventsel;
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unsigned perfctr;
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u64 (*event_map)(int);
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@ -845,7 +845,7 @@ void hw_perf_enable(void)
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set_bit(hwc->idx, cpuc->active_mask);
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cpuc->events[hwc->idx] = event;
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x86_pmu.enable(hwc, hwc->idx);
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x86_pmu.enable(event);
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perf_event_update_userpage(event);
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}
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cpuc->n_added = 0;
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@ -858,15 +858,16 @@ void hw_perf_enable(void)
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x86_pmu.enable_all();
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}
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static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
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{
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(void)checking_wrmsrl(hwc->config_base + idx,
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(void)checking_wrmsrl(hwc->config_base + hwc->idx,
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hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
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}
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static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
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static inline void x86_pmu_disable_event(struct perf_event *event)
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{
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(void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
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struct hw_perf_event *hwc = &event->hw;
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(void)checking_wrmsrl(hwc->config_base + hwc->idx, hwc->config);
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}
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static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
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@ -927,11 +928,11 @@ x86_perf_event_set_period(struct perf_event *event)
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return ret;
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}
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static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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static void x86_pmu_enable_event(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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if (cpuc->enabled)
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__x86_pmu_enable_event(hwc, idx);
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__x86_pmu_enable_event(&event->hw);
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}
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/*
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@ -974,13 +975,11 @@ static int x86_pmu_enable(struct perf_event *event)
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static int x86_pmu_start(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (hwc->idx == -1)
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if (event->hw.idx == -1)
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return -EAGAIN;
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x86_perf_event_set_period(event);
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x86_pmu.enable(hwc, hwc->idx);
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x86_pmu.enable(event);
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return 0;
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}
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@ -994,7 +993,7 @@ static void x86_pmu_unthrottle(struct perf_event *event)
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cpuc->events[hwc->idx] != event))
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return;
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x86_pmu.enable(hwc, hwc->idx);
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x86_pmu.enable(event);
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}
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void perf_event_print_debug(void)
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@ -1059,7 +1058,7 @@ static void x86_pmu_stop(struct perf_event *event)
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* could reenable again:
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*/
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clear_bit(idx, cpuc->active_mask);
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x86_pmu.disable(hwc, idx);
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x86_pmu.disable(event);
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/*
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* Drain the remaining delta count out of a event
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@ -1127,7 +1126,7 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
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continue;
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if (perf_event_overflow(event, 1, &data, regs))
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x86_pmu.disable(hwc, idx);
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x86_pmu.disable(event);
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}
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if (handled)
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@ -548,9 +548,9 @@ static inline void intel_pmu_ack_status(u64 ack)
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}
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static inline void
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intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
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intel_pmu_disable_fixed(struct hw_perf_event *hwc)
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{
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int idx = __idx - X86_PMC_IDX_FIXED;
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int idx = hwc->idx - X86_PMC_IDX_FIXED;
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u64 ctrl_val, mask;
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mask = 0xfULL << (idx * 4);
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@ -621,26 +621,28 @@ static void intel_pmu_drain_bts_buffer(void)
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}
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static inline void
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intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
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intel_pmu_disable_event(struct perf_event *event)
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{
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if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
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struct hw_perf_event *hwc = &event->hw;
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if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
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intel_pmu_disable_bts();
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intel_pmu_drain_bts_buffer();
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return;
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}
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
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intel_pmu_disable_fixed(hwc, idx);
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intel_pmu_disable_fixed(hwc);
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return;
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}
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x86_pmu_disable_event(hwc, idx);
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x86_pmu_disable_event(event);
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}
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static inline void
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intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
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intel_pmu_enable_fixed(struct hw_perf_event *hwc)
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{
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int idx = __idx - X86_PMC_IDX_FIXED;
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int idx = hwc->idx - X86_PMC_IDX_FIXED;
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u64 ctrl_val, bits, mask;
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int err;
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@ -670,9 +672,11 @@ intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
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err = checking_wrmsrl(hwc->config_base, ctrl_val);
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}
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static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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static void intel_pmu_enable_event(struct perf_event *event)
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{
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if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
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struct hw_perf_event *hwc = &event->hw;
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if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
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if (!__get_cpu_var(cpu_hw_events).enabled)
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return;
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@ -681,11 +685,11 @@ static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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}
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
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intel_pmu_enable_fixed(hwc, idx);
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intel_pmu_enable_fixed(hwc);
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return;
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}
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__x86_pmu_enable_event(hwc, idx);
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__x86_pmu_enable_event(hwc);
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}
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/*
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@ -771,7 +775,7 @@ again:
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data.period = event->hw.last_period;
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if (perf_event_overflow(event, 1, &data, regs))
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intel_pmu_disable_event(&event->hw, bit);
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intel_pmu_disable_event(event);
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}
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intel_pmu_ack_status(ack);
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@ -77,27 +77,29 @@ static void p6_pmu_enable_all(void)
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}
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static inline void
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p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
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p6_pmu_disable_event(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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u64 val = P6_NOP_EVENT;
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if (cpuc->enabled)
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val |= ARCH_PERFMON_EVENTSEL_ENABLE;
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(void)checking_wrmsrl(hwc->config_base + idx, val);
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(void)checking_wrmsrl(hwc->config_base + hwc->idx, val);
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}
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static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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static void p6_pmu_enable_event(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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u64 val;
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val = hwc->config;
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if (cpuc->enabled)
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val |= ARCH_PERFMON_EVENTSEL_ENABLE;
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(void)checking_wrmsrl(hwc->config_base + idx, val);
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(void)checking_wrmsrl(hwc->config_base + hwc->idx, val);
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}
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static __initconst struct x86_pmu p6_pmu = {
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