mtd: spi-nor: intel: remove global protection flag
For the Atmel and SST parts this flag was already moved to individual flash parts because it is considered bad esp. because newer flash chips will automatically inherit the "has locking" support. While this won't likely be the case for the Intel parts, we do it for consistency reasons. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20201203162959.29589-6-michael@walle.cc
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@ -10,23 +10,13 @@
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static const struct flash_info intel_parts[] = {
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/* Intel/Numonyx -- xxxs33b */
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{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
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{ "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
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{ "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
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};
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static void intel_default_init(struct spi_nor *nor)
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{
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nor->flags |= SNOR_F_HAS_LOCK;
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}
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static const struct spi_nor_fixups intel_fixups = {
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.default_init = intel_default_init,
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{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, SPI_NOR_HAS_LOCK) },
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{ "320s33b", INFO(0x898912, 0, 64 * 1024, 64, SPI_NOR_HAS_LOCK) },
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{ "640s33b", INFO(0x898913, 0, 64 * 1024, 128, SPI_NOR_HAS_LOCK) },
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};
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const struct spi_nor_manufacturer spi_nor_intel = {
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.name = "intel",
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.parts = intel_parts,
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.nparts = ARRAY_SIZE(intel_parts),
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.fixups = &intel_fixups,
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};
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