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soc: sifive: ccache: define the macro for the register shifts

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Define the macro for the register shifts, it could make the code be
more readable

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Zong Li 2022-09-13 06:18:16 +00:00 committed by Palmer Dabbelt
parent 696ab9bda2
commit afc7a5834f
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
1 changed files with 11 additions and 5 deletions
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16
drivers/soc/sifive/sifive_ccache.c
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@ -13,6 +13,7 @@
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/device.h>
#include <linux/bitfield.h>
#include <asm/cacheinfo.h>
#include <soc/sifive/sifive_ccache.h>
@ -33,6 +34,11 @@
#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
#define SIFIVE_CCACHE_CONFIG 0x00
#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)
#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)
#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
#define SIFIVE_CCACHE_WAYENABLE 0x08
#define SIFIVE_CCACHE_ECCINJECTERR 0x40
@ -87,11 +93,11 @@ static void ccache_config_read(void)
u32 cfg;
cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
(cfg & 0xff), (cfg >> 8) & 0xff,
BIT_ULL((cfg >> 16) & 0xff),
BIT_ULL((cfg >> 24) & 0xff));
pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",
FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),
FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),
BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
pr_info("Index of the largest way enabled: %u\n", cfg);