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drm: bridge: cdns-mhdp8546: Add TI J721E wrapper

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Add J721E wrapper for mhdp, which sets up the clock and data muxes.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Swapnil Jakhade 2020-09-18 14:09:23 +02:00 committed by Tomi Valkeinen
parent fb43aa0acd
commit afba7e6c5f
6 changed files with 122 additions and 0 deletions
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13
drivers/gpu/drm/bridge/cadence/Kconfig
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@ -9,3 +9,16 @@ config DRM_CDNS_MHDP8546
bridge and is meant to be directly embedded in a SoC.
It takes a DPI stream as input and outputs it encoded
in DP format.
if DRM_CDNS_MHDP8546
config DRM_CDNS_MHDP8546_J721E
depends on ARCH_K3_J721E_SOC || COMPILE_TEST
bool "J721E Cadence DPI/DP wrapper support"
default y
help
Support J721E Cadence DPI/DP wrapper. This is a wrapper
which adds support for J721E related platform ops. It
initializes the J721E Display Port and sets up the
clock and data muxes.
endif

1
drivers/gpu/drm/bridge/cadence/Makefile
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@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o

10
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
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@ -50,6 +50,8 @@
#include "cdns-mhdp8546-core.h"
#include "cdns-mhdp8546-j721e.h"
static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
{
int ret, empty;
@ -2496,6 +2498,14 @@ static int cdns_mhdp_remove(struct platform_device *pdev)
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
#ifdef CONFIG_DRM_CDNS_MHDP8546_J721E
{ .compatible = "ti,j721e-mhdp8546",
.data = &(const struct cdns_mhdp_platform_info) {
.timings = &mhdp_ti_j721e_bridge_timings,
.ops = &mhdp_ti_j721e_ops,
},
},
#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);

1
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
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@ -341,6 +341,7 @@ struct cdns_mhdp_platform_info {
struct cdns_mhdp_device {
void __iomem *regs;
void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;

78
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c Normal file
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@ -0,0 +1,78 @@
// SPDX-License-Identifier: GPL-2.0
/*
* TI j721e Cadence MHDP8546 DP wrapper
*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
* Author: Jyri Sarha <jsarha@ti.com>
*/
#include <linux/io.h>
#include <linux/platform_device.h>
#include "cdns-mhdp8546-j721e.h"
#define REVISION 0x00
#define DPTX_IPCFG 0x04
#define ECC_MEM_CFG 0x08
#define DPTX_DSC_CFG 0x0c
#define DPTX_SRC_CFG 0x10
#define DPTX_VIF_SECURE_MODE_CFG 0x14
#define DPTX_VIF_CONN_STATUS 0x18
#define PHY_CLK_STATUS 0x1c
#define DPTX_SRC_AIF_EN BIT(16)
#define DPTX_SRC_VIF_3_IN30B BIT(11)
#define DPTX_SRC_VIF_2_IN30B BIT(10)
#define DPTX_SRC_VIF_1_IN30B BIT(9)
#define DPTX_SRC_VIF_0_IN30B BIT(8)
#define DPTX_SRC_VIF_3_SEL_DPI5 BIT(7)
#define DPTX_SRC_VIF_3_SEL_DPI3 0
#define DPTX_SRC_VIF_2_SEL_DPI4 BIT(6)
#define DPTX_SRC_VIF_2_SEL_DPI2 0
#define DPTX_SRC_VIF_1_SEL_DPI3 BIT(5)
#define DPTX_SRC_VIF_1_SEL_DPI1 0
#define DPTX_SRC_VIF_0_SEL_DPI2 BIT(4)
#define DPTX_SRC_VIF_0_SEL_DPI0 0
#define DPTX_SRC_VIF_3_EN BIT(3)
#define DPTX_SRC_VIF_2_EN BIT(2)
#define DPTX_SRC_VIF_1_EN BIT(1)
#define DPTX_SRC_VIF_0_EN BIT(0)
/* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
static int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
{
struct platform_device *pdev = to_platform_device(mhdp->dev);
mhdp->j721e_regs = devm_platform_ioremap_resource(pdev, 1);
return PTR_ERR_OR_ZERO(mhdp->j721e_regs);
}
static void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)
{
/*
* Enable VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected
* to eDP DPI2. This is the only supported SST configuration on
* J721E.
*/
writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
mhdp->j721e_regs + DPTX_SRC_CFG);
}
static void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)
{
/* Put everything to defaults */
writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
}
const struct mhdp_platform_ops mhdp_ti_j721e_ops = {
.init = cdns_mhdp_j721e_init,
.enable = cdns_mhdp_j721e_enable,
.disable = cdns_mhdp_j721e_disable,
};
const struct drm_bridge_timings mhdp_ti_j721e_bridge_timings = {
.input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE |
DRM_BUS_FLAG_DE_HIGH,
};

19
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.h Normal file
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@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* TI j721e Cadence MHDP8546 DP wrapper
*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
* Author: Jyri Sarha <jsarha@ti.com>
*/
#ifndef CDNS_MHDP8546_J721E_H
#define CDNS_MHDP8546_J721E_H
#include "cdns-mhdp8546-core.h"
struct mhdp_platform_ops;
extern const struct mhdp_platform_ops mhdp_ti_j721e_ops;
extern const struct drm_bridge_timings mhdp_ti_j721e_bridge_timings;
#endif /* !CDNS_MHDP8546_J721E_H */