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drm/i915: Implement read-only support in whitelist selftest

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Newer hardware supports extra feature in the whitelist registers. This
patch updates the selftest to test that entries marked as read only
are actually read only.

v2: Removed all use of 'rsvd' for read-only registers to avoid
ambiguous code or error messages.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
CC: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190712070745.35239-3-John.C.Harrison@Intel.com
This commit is contained in:
John Harrison 2019-07-12 00:07:44 -07:00 committed by Tvrtko Ursulin
parent 1e2b7f497c
commit aee20aaed8
1 changed files with 35 additions and 14 deletions
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49
drivers/gpu/drm/i915/gt/selftest_workarounds.c
View File

@ -485,12 +485,12 @@ static int check_dirty_whitelist(struct i915_gem_context *ctx,
u32 srm, lrm, rsvd;
u32 expect;
int idx;
bool ro_reg;
if (wo_register(engine, reg))
continue;
if (ro_register(reg))
continue;
ro_reg = ro_register(reg);
srm = MI_STORE_REGISTER_MEM;
lrm = MI_LOAD_REGISTER_MEM;
@ -591,24 +591,35 @@ err_request:
}
GEM_BUG_ON(values[ARRAY_SIZE(values) - 1] != 0xffffffff);
rsvd = results[ARRAY_SIZE(values)]; /* detect write masking */
if (!rsvd) {
pr_err("%s: Unable to write to whitelisted register %x\n",
engine->name, reg);
err = -EINVAL;
goto out_unpin;
if (!ro_reg) {
/* detect write masking */
rsvd = results[ARRAY_SIZE(values)];
if (!rsvd) {
pr_err("%s: Unable to write to whitelisted register %x\n",
engine->name, reg);
err = -EINVAL;
goto out_unpin;
}
}
expect = results[0];
idx = 1;
for (v = 0; v < ARRAY_SIZE(values); v++) {
expect = reg_write(expect, values[v], rsvd);
if (ro_reg)
expect = results[0];
else
expect = reg_write(expect, values[v], rsvd);
if (results[idx] != expect)
err++;
idx++;
}
for (v = 0; v < ARRAY_SIZE(values); v++) {
expect = reg_write(expect, ~values[v], rsvd);
if (ro_reg)
expect = results[0];
else
expect = reg_write(expect, ~values[v], rsvd);
if (results[idx] != expect)
err++;
idx++;
@ -617,15 +628,22 @@ err_request:
pr_err("%s: %d mismatch between values written to whitelisted register [%x], and values read back!\n",
engine->name, err, reg);
pr_info("%s: Whitelisted register: %x, original value %08x, rsvd %08x\n",
engine->name, reg, results[0], rsvd);
if (ro_reg)
pr_info("%s: Whitelisted read-only register: %x, original value %08x\n",
engine->name, reg, results[0]);
else
pr_info("%s: Whitelisted register: %x, original value %08x, rsvd %08x\n",
engine->name, reg, results[0], rsvd);
expect = results[0];
idx = 1;
for (v = 0; v < ARRAY_SIZE(values); v++) {
u32 w = values[v];
expect = reg_write(expect, w, rsvd);
if (ro_reg)
expect = results[0];
else
expect = reg_write(expect, w, rsvd);
pr_info("Wrote %08x, read %08x, expect %08x\n",
w, results[idx], expect);
idx++;
@ -633,7 +651,10 @@ err_request:
for (v = 0; v < ARRAY_SIZE(values); v++) {
u32 w = ~values[v];
expect = reg_write(expect, w, rsvd);
if (ro_reg)
expect = results[0];
else
expect = reg_write(expect, w, rsvd);
pr_info("Wrote %08x, read %08x, expect %08x\n",
w, results[idx], expect);
idx++;