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drm/msm/dpu: stop embedding dpu_hw_blk into dpu_hw_intf

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Now as dpu_hw_intf is not hanled by dpu_rm_get_assigned_resources, there
is no point in embedding the (empty) struct dpu_hw_blk into dpu_hw_intf
(and using typecasts between dpu_hw_blk and dpu_hw_intf). Drop it and
use dpu_hw_intf directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Link: https://lore.kernel.org/r/20220121210618.3482550-5-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Dmitry Baryshkov 2022-01-22 00:06:16 +03:00
parent ef58e0ad34
commit ae57fdf0f2
3 changed files with 9 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
View File

@ -78,7 +78,6 @@ struct dpu_hw_intf_ops {
};
struct dpu_hw_intf {
struct dpu_hw_blk base;
struct dpu_hw_blk_reg_map hw;
/* intf */
@ -90,16 +89,6 @@ struct dpu_hw_intf {
struct dpu_hw_intf_ops ops;
};
/**
* to_dpu_hw_intf - convert base object dpu_hw_base to container
* @hw: Pointer to base hardware block
* return: Pointer to hardware block container
*/
static inline struct dpu_hw_intf *to_dpu_hw_intf(struct dpu_hw_blk *hw)
{
return container_of(hw, struct dpu_hw_intf, base);
}
/**
* dpu_hw_intf_init(): Initializes the intf driver for the passed
* interface idx.

17
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
View File

@ -74,14 +74,8 @@ int dpu_rm_destroy(struct dpu_rm *rm)
dpu_hw_ctl_destroy(hw);
}
}
for (i = 0; i < ARRAY_SIZE(rm->intf_blks); i++) {
struct dpu_hw_intf *hw;
if (rm->intf_blks[i]) {
hw = to_dpu_hw_intf(rm->intf_blks[i]);
dpu_hw_intf_destroy(hw);
}
}
for (i = 0; i < ARRAY_SIZE(rm->hw_intf); i++)
dpu_hw_intf_destroy(rm->hw_intf[i]);
return 0;
}
@ -179,7 +173,7 @@ int dpu_rm_init(struct dpu_rm *rm,
DPU_ERROR("failed intf object creation: err %d\n", rc);
goto fail;
}
rm->intf_blks[intf->id - INTF_0] = &hw->base;
rm->hw_intf[intf->id - INTF_0] = hw;
}
for (i = 0; i < cat->ctl_count; i++) {
@ -593,8 +587,3 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
return num_blks;
}
struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
{
return to_dpu_hw_intf(rm->intf_blks[intf_idx - INTF_0]);
}

9
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
View File

@ -18,14 +18,14 @@ struct dpu_global_state;
* @pingpong_blks: array of pingpong hardware resources
* @mixer_blks: array of layer mixer hardware resources
* @ctl_blks: array of ctl hardware resources
* @intf_blks: array of intf hardware resources
* @hw_intf: array of intf hardware resources
* @dspp_blks: array of dspp hardware resources
*/
struct dpu_rm {
struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
};
@ -90,7 +90,10 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
* @rm: DPU Resource Manager handle
* @intf_idx: INTF's index
*/
struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx);
static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
{
return rm->hw_intf[intf_idx - INTF_0];
}
#endif /* __DPU_RM_H__ */