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[ARM] 4519/1: S3C: split S3C2400 values out of S3C24XX map.h

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Move the S3C2400 values to their own include directory
series in include/asm-arm/arch-s3c2400 as the support
for the S3C2400 is best placed in its own arch directory.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks 2007-07-22 16:18:22 +01:00 committed by Russell King
parent a45f82616e
commit ae39ae0b00
2 changed files with 66 additions and 51 deletions
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66
include/asm-arm/arch-s3c2400/map.h Normal file
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@ -0,0 +1,66 @@
/* linux/include/asm-arm/arch-s3c2400/map.h
*
* Copyright 2003,2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* Copyright 2003, Lucas Correia Villa Real
*
* S3C2400 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C2400_PA_MEMCTRL (0x14000000)
#define S3C2400_PA_USBHOST (0x14200000)
#define S3C2400_PA_IRQ (0x14400000)
#define S3C2400_PA_DMA (0x14600000)
#define S3C2400_PA_CLKPWR (0x14800000)
#define S3C2400_PA_LCD (0x14A00000)
#define S3C2400_PA_UART (0x15000000)
#define S3C2400_PA_TIMER (0x15100000)
#define S3C2400_PA_USBDEV (0x15200140)
#define S3C2400_PA_WATCHDOG (0x15300000)
#define S3C2400_PA_IIC (0x15400000)
#define S3C2400_PA_IIS (0x15508000)
#define S3C2400_PA_GPIO (0x15600000)
#define S3C2400_PA_RTC (0x15700040)
#define S3C2400_PA_ADC (0x15800000)
#define S3C2400_PA_SPI (0x15900000)
#define S3C2400_PA_MMC (0x15A00000)
#define S3C2400_SZ_MMC SZ_1M
/* physical addresses of all the chip-select areas */
#define S3C2400_CS0 (0x00000000)
#define S3C2400_CS1 (0x02000000)
#define S3C2400_CS2 (0x04000000)
#define S3C2400_CS3 (0x06000000)
#define S3C2400_CS4 (0x08000000)
#define S3C2400_CS5 (0x0A000000)
#define S3C2400_CS6 (0x0C000000)
#define S3C2400_CS7 (0x0E000000)
#define S3C2400_SDRAM_PA (S3C2400_CS6)
/* Use a single interface for common resources between S3C24XX cpus */
#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
#define S3C24XX_PA_DMA S3C2400_PA_DMA
#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
#define S3C24XX_PA_LCD S3C2400_PA_LCD
#define S3C24XX_PA_UART S3C2400_PA_UART
#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C2400_PA_IIC
#define S3C24XX_PA_IIS S3C2400_PA_IIS
#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
#define S3C24XX_PA_RTC S3C2400_PA_RTC
#define S3C24XX_PA_ADC S3C2400_PA_ADC
#define S3C24XX_PA_SPI S3C2400_PA_SPI

51
include/asm-arm/arch-s3c2410/map.h
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@ -30,41 +30,33 @@
#define S3C2410_ADDR(x) (0xF0000000 + (x)) #define S3C2410_ADDR(x) (0xF0000000 + (x))
#endif #endif
#define S3C2400_ADDR(x) S3C2410_ADDR(x)
/* interrupt controller is the first thing we put in, to make /* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier * the assembly code for the irq detection easier
*/ */
#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000) #define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
#define S3C2400_PA_IRQ (0x14400000)
#define S3C2410_PA_IRQ (0x4A000000) #define S3C2410_PA_IRQ (0x4A000000)
#define S3C24XX_SZ_IRQ SZ_1M #define S3C24XX_SZ_IRQ SZ_1M
/* memory controller registers */ /* memory controller registers */
#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000) #define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
#define S3C2400_PA_MEMCTRL (0x14000000)
#define S3C2410_PA_MEMCTRL (0x48000000) #define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C24XX_SZ_MEMCTRL SZ_1M #define S3C24XX_SZ_MEMCTRL SZ_1M
/* USB host controller */ /* USB host controller */
#define S3C2400_PA_USBHOST (0x14200000)
#define S3C2410_PA_USBHOST (0x49000000) #define S3C2410_PA_USBHOST (0x49000000)
#define S3C24XX_SZ_USBHOST SZ_1M #define S3C24XX_SZ_USBHOST SZ_1M
/* DMA controller */ /* DMA controller */
#define S3C2400_PA_DMA (0x14600000)
#define S3C2410_PA_DMA (0x4B000000) #define S3C2410_PA_DMA (0x4B000000)
#define S3C24XX_SZ_DMA SZ_1M #define S3C24XX_SZ_DMA SZ_1M
/* Clock and Power management */ /* Clock and Power management */
#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000) #define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000)
#define S3C2400_PA_CLKPWR (0x14800000)
#define S3C2410_PA_CLKPWR (0x4C000000) #define S3C2410_PA_CLKPWR (0x4C000000)
#define S3C24XX_SZ_CLKPWR SZ_1M #define S3C24XX_SZ_CLKPWR SZ_1M
/* LCD controller */ /* LCD controller */
#define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000) #define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000)
#define S3C2400_PA_LCD (0x14A00000)
#define S3C2410_PA_LCD (0x4D000000) #define S3C2410_PA_LCD (0x4D000000)
#define S3C24XX_SZ_LCD SZ_1M #define S3C24XX_SZ_LCD SZ_1M
@ -72,41 +64,31 @@
#define S3C2410_PA_NAND (0x4E000000) #define S3C2410_PA_NAND (0x4E000000)
#define S3C24XX_SZ_NAND SZ_1M #define S3C24XX_SZ_NAND SZ_1M
/* MMC controller - available on the S3C2400 */
#define S3C2400_PA_MMC (0x15A00000)
#define S3C2400_SZ_MMC SZ_1M
/* UARTs */ /* UARTs */
#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000) #define S3C24XX_VA_UART S3C2410_ADDR(0x00400000)
#define S3C2400_PA_UART (0x15000000)
#define S3C2410_PA_UART (0x50000000) #define S3C2410_PA_UART (0x50000000)
#define S3C24XX_SZ_UART SZ_1M #define S3C24XX_SZ_UART SZ_1M
/* Timers */ /* Timers */
#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000) #define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000)
#define S3C2400_PA_TIMER (0x15100000)
#define S3C2410_PA_TIMER (0x51000000) #define S3C2410_PA_TIMER (0x51000000)
#define S3C24XX_SZ_TIMER SZ_1M #define S3C24XX_SZ_TIMER SZ_1M
/* USB Device port */ /* USB Device port */
#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000) #define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000)
#define S3C2400_PA_USBDEV (0x15200140)
#define S3C2410_PA_USBDEV (0x52000000) #define S3C2410_PA_USBDEV (0x52000000)
#define S3C24XX_SZ_USBDEV SZ_1M #define S3C24XX_SZ_USBDEV SZ_1M
/* Watchdog */ /* Watchdog */
#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000) #define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
#define S3C2400_PA_WATCHDOG (0x15300000)
#define S3C2410_PA_WATCHDOG (0x53000000) #define S3C2410_PA_WATCHDOG (0x53000000)
#define S3C24XX_SZ_WATCHDOG SZ_1M #define S3C24XX_SZ_WATCHDOG SZ_1M
/* IIC hardware controller */ /* IIC hardware controller */
#define S3C2400_PA_IIC (0x15400000)
#define S3C2410_PA_IIC (0x54000000) #define S3C2410_PA_IIC (0x54000000)
#define S3C24XX_SZ_IIC SZ_1M #define S3C24XX_SZ_IIC SZ_1M
/* IIS controller */ /* IIS controller */
#define S3C2400_PA_IIS (0x15508000)
#define S3C2410_PA_IIS (0x55000000) #define S3C2410_PA_IIS (0x55000000)
#define S3C24XX_SZ_IIS SZ_1M #define S3C24XX_SZ_IIS SZ_1M
@ -120,23 +102,19 @@
* by the base system. * by the base system.
*/ */
#define S3C2400_PA_GPIO (0x15600000)
#define S3C2410_PA_GPIO (0x56000000) #define S3C2410_PA_GPIO (0x56000000)
#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) #define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
#define S3C24XX_SZ_GPIO SZ_1M #define S3C24XX_SZ_GPIO SZ_1M
/* RTC */ /* RTC */
#define S3C2400_PA_RTC (0x15700040)
#define S3C2410_PA_RTC (0x57000000) #define S3C2410_PA_RTC (0x57000000)
#define S3C24XX_SZ_RTC SZ_1M #define S3C24XX_SZ_RTC SZ_1M
/* ADC */ /* ADC */
#define S3C2400_PA_ADC (0x15800000)
#define S3C2410_PA_ADC (0x58000000) #define S3C2410_PA_ADC (0x58000000)
#define S3C24XX_SZ_ADC SZ_1M #define S3C24XX_SZ_ADC SZ_1M
/* SPI */ /* SPI */
#define S3C2400_PA_SPI (0x15900000)
#define S3C2410_PA_SPI (0x59000000) #define S3C2410_PA_SPI (0x59000000)
#define S3C24XX_SZ_SPI SZ_1M #define S3C24XX_SZ_SPI SZ_1M
@ -177,37 +155,9 @@
#define S3C2410_SDRAM_PA (S3C2410_CS6) #define S3C2410_SDRAM_PA (S3C2410_CS6)
#define S3C2400_CS0 (0x00000000)
#define S3C2400_CS1 (0x02000000)
#define S3C2400_CS2 (0x04000000)
#define S3C2400_CS3 (0x06000000)
#define S3C2400_CS4 (0x08000000)
#define S3C2400_CS5 (0x0A000000)
#define S3C2400_CS6 (0x0C000000)
#define S3C2400_CS7 (0x0E000000)
#define S3C2400_SDRAM_PA (S3C2400_CS6)
/* Use a single interface for common resources between S3C24XX cpus */ /* Use a single interface for common resources between S3C24XX cpus */
#ifdef CONFIG_CPU_S3C2400
#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
#define S3C24XX_PA_DMA S3C2400_PA_DMA
#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
#define S3C24XX_PA_LCD S3C2400_PA_LCD
#define S3C24XX_PA_UART S3C2400_PA_UART
#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C2400_PA_IIC
#define S3C24XX_PA_IIS S3C2400_PA_IIS
#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
#define S3C24XX_PA_RTC S3C2400_PA_RTC
#define S3C24XX_PA_ADC S3C2400_PA_ADC
#define S3C24XX_PA_SPI S3C2400_PA_SPI
#else
#define S3C24XX_PA_IRQ S3C2410_PA_IRQ #define S3C24XX_PA_IRQ S3C2410_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST #define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
@ -224,7 +174,6 @@
#define S3C24XX_PA_RTC S3C2410_PA_RTC #define S3C24XX_PA_RTC S3C2410_PA_RTC
#define S3C24XX_PA_ADC S3C2410_PA_ADC #define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI #define S3C24XX_PA_SPI S3C2410_PA_SPI
#endif
/* deal with the registers that move under the 2412/2413 */ /* deal with the registers that move under the 2412/2413 */