drm/i915/fbc: Parametrize FBC register offsets
Parametrize ilk+ FBC register offsets based on the FBC instance. v2: More intel_ namespace (Jani) v3: Don't break gvt (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211214184616.1410-1-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä
parent
a908db6d98
commit
ae361eb07e
@ -85,6 +85,8 @@ struct intel_fbc {
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struct drm_mm_node compressed_fb;
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struct drm_mm_node compressed_llb;
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enum intel_fbc_id id;
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u8 limit;
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bool false_color;
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@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
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struct intel_fbc_state *fbc_state = &fbc->state;
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struct drm_i915_private *i915 = fbc->i915;
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intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
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intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
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fbc_state->fence_y_offset);
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intel_de_write(i915, ILK_DPFC_CONTROL,
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intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
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DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
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}
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@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
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u32 dpfc_ctl;
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/* Disable compression */
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dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
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dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
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if (dpfc_ctl & DPFC_CTL_EN) {
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dpfc_ctl &= ~DPFC_CTL_EN;
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intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
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intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
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}
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}
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static bool ilk_fbc_is_active(struct intel_fbc *fbc)
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{
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return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
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return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
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}
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static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
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{
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return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
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return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
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}
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static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
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{
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struct drm_i915_private *i915 = fbc->i915;
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intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
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intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
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}
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static const struct intel_fbc_funcs ilk_fbc_funcs = {
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@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
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{
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struct drm_i915_private *i915 = fbc->i915;
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intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
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intel_de_posting_read(i915, MSG_FBC_REND_STATE);
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intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
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intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
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}
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static const struct intel_fbc_funcs snb_fbc_funcs = {
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@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
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val |= FBC_STRIDE_OVERRIDE |
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FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
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intel_de_write(i915, GLK_FBC_STRIDE, val);
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intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
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}
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static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
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@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
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if (i915->ggtt.num_fences)
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snb_fbc_program_fence(fbc);
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intel_de_write(i915, ILK_DPFC_CONTROL,
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intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
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DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
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}
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static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
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{
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return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB;
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return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
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}
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static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
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bool enable)
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{
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intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
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intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
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DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
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}
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@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
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fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
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}
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static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
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static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
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enum intel_fbc_id fbc_id)
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{
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struct intel_fbc *fbc;
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@ -1628,6 +1631,7 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
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if (!fbc)
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return NULL;
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fbc->id = fbc_id;
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fbc->i915 = i915;
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INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
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mutex_init(&fbc->lock);
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@ -1671,7 +1675,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
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if (!HAS_FBC(i915))
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return;
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fbc = intel_fbc_create(i915);
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fbc = intel_fbc_create(i915, INTEL_FBC_A);
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if (!fbc)
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return;
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@ -17,6 +17,12 @@ struct intel_fbc;
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struct intel_plane;
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struct intel_plane_state;
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enum intel_fbc_id {
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INTEL_FBC_A,
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I915_MAX_FBCS,
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};
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int intel_fbc_atomic_check(struct intel_atomic_state *state);
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bool intel_fbc_pre_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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@ -40,6 +40,7 @@
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#include "gvt.h"
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#include "i915_pvinfo.h"
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#include "display/intel_display_types.h"
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#include "display/intel_fbc.h"
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/* XXX FIXME i915 has changed PP_XXX definition */
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#define PCH_PP_STATUS _MMIO(0xc7200)
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@ -2647,12 +2648,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
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MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
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MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
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MMIO_D(ILK_DPFC_CONTROL, D_ALL);
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MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
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MMIO_D(ILK_DPFC_STATUS, D_ALL);
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MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
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MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
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MMIO_D(ILK_DPFC_CB_BASE(INTEL_FBC_A), D_ALL);
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MMIO_D(ILK_DPFC_CONTROL(INTEL_FBC_A), D_ALL);
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MMIO_D(ILK_DPFC_RECOMP_CTL(INTEL_FBC_A), D_ALL);
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MMIO_D(ILK_DPFC_STATUS(INTEL_FBC_A), D_ALL);
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MMIO_D(ILK_DPFC_FENCE_YOFF(INTEL_FBC_A), D_ALL);
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MMIO_D(ILK_DPFC_CHICKEN(INTEL_FBC_A), D_ALL);
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MMIO_D(ILK_FBC_RT_BASE, D_ALL);
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MMIO_D(IPS_CTL, D_ALL);
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@ -3353,10 +3353,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define FBC_LL_SIZE (1536)
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/* Framebuffer compression for GM45+ */
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#define DPFC_CB_BASE _MMIO(0x3200)
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#define ILK_DPFC_CB_BASE _MMIO(0x43200)
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#define DPFC_CONTROL _MMIO(0x3208)
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#define ILK_DPFC_CONTROL _MMIO(0x43208)
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#define DPFC_CB_BASE _MMIO(0x3200)
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#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
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#define DPFC_CONTROL _MMIO(0x3208)
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#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
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#define DPFC_CTL_EN REG_BIT(31)
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#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
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#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
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@ -3374,28 +3374,28 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
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#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
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#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
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#define DPFC_RECOMP_CTL _MMIO(0x320c)
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#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
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#define DPFC_RECOMP_CTL _MMIO(0x320c)
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#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
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#define DPFC_RECOMP_STALL_EN REG_BIT(27)
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#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
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#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
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#define DPFC_STATUS _MMIO(0x3210)
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#define ILK_DPFC_STATUS _MMIO(0x43210)
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#define DPFC_STATUS _MMIO(0x3210)
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#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
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#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
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#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
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#define DPFC_STATUS2 _MMIO(0x3214)
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#define ILK_DPFC_STATUS2 _MMIO(0x43214)
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#define DPFC_STATUS2 _MMIO(0x3214)
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#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
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#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
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#define DPFC_FENCE_YOFF _MMIO(0x3218)
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#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
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#define DPFC_CHICKEN _MMIO(0x3224)
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#define ILK_DPFC_CHICKEN _MMIO(0x43224)
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#define DPFC_FENCE_YOFF _MMIO(0x3218)
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#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
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#define DPFC_CHICKEN _MMIO(0x3224)
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#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
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#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
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#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
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#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
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#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
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#define GLK_FBC_STRIDE _MMIO(0x43228)
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#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
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#define FBC_STRIDE_OVERRIDE REG_BIT(15)
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#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
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#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
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@ -3438,9 +3438,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define IPS_CTL _MMIO(0x43408)
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#define IPS_ENABLE (1 << 31)
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#define MSG_FBC_REND_STATE _MMIO(0x50380)
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#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
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#define FBC_REND_NUKE REG_BIT(2)
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#define FBC_REND_CACHE_CLEAN REG_BIT(1)
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#define FBC_REND_CACHE_CLEAN REG_BIT(1)
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/*
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* GPIO regs
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@ -160,8 +160,9 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
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* WaFbcHighMemBwCorruptionAvoidance:bxt
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* Display WA #0883: bxt
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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DPFC_DISABLE_DUMMY0);
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
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DPFC_DISABLE_DUMMY0);
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}
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static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
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@ -7451,8 +7452,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
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static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
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{
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/* Wa_1409120013:icl,ehl */
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
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DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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/*Wa_14010594013:icl, ehl */
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intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
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@ -7464,7 +7465,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
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/* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
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if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
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IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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/* Wa_1409825376:tgl (pre-prod)*/
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@ -7526,8 +7527,9 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
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* WaFbcNukeOnHostModify:cfl
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* Display WA #0873: cfl
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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DPFC_NUKE_ON_ANY_MODIFICATION);
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
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DPFC_NUKE_ON_ANY_MODIFICATION);
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}
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static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
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@ -7559,8 +7561,9 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
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* WaFbcNukeOnHostModify:kbl
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* Display WA #0873: kbl
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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DPFC_NUKE_ON_ANY_MODIFICATION);
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
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DPFC_NUKE_ON_ANY_MODIFICATION);
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}
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static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
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@ -7586,15 +7589,17 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
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* WaFbcNukeOnHostModify:skl
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* Display WA #0873: skl
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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DPFC_NUKE_ON_ANY_MODIFICATION);
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
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DPFC_NUKE_ON_ANY_MODIFICATION);
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/*
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* WaFbcHighMemBwCorruptionAvoidance:skl
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* Display WA #0883: skl
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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DPFC_DISABLE_DUMMY0);
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
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intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
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DPFC_DISABLE_DUMMY0);
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}
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static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
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