forked from Minki/linux
iommu/arm-smmu: Convert to iommu_fwspec
In the final step of preparation for full generic configuration support, swap our fixed-size master_cfg for the generic iommu_fwspec. For the legacy DT bindings, the driver simply gets to act as its own 'firmware'. Farewell, arbitrary MAX_MASTER_STREAMIDS! Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
Will Deacon
parent
588888a739
commit
adfec2e709
@ -42,6 +42,7 @@
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_iommu.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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@ -51,9 +52,6 @@
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#include "io-pgtable.h"
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/* Maximum number of stream IDs assigned to a single device */
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#define MAX_MASTER_STREAMIDS 128
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/* Maximum number of context banks per SMMU */
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#define ARM_SMMU_MAX_CBS 128
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@ -321,13 +319,13 @@ struct arm_smmu_smr {
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struct arm_smmu_master_cfg {
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struct arm_smmu_device *smmu;
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int num_streamids;
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u16 streamids[MAX_MASTER_STREAMIDS];
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s16 smendx[MAX_MASTER_STREAMIDS];
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s16 smendx[];
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};
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#define INVALID_SMENDX -1
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#define for_each_cfg_sme(cfg, i, idx) \
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for (i = 0; idx = cfg->smendx[i], i < cfg->num_streamids; ++i)
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#define __fwspec_cfg(fw) ((struct arm_smmu_master_cfg *)fw->iommu_priv)
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#define fwspec_smmu(fw) (__fwspec_cfg(fw)->smmu)
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#define for_each_cfg_sme(fw, i, idx) \
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for (i = 0; idx = __fwspec_cfg(fw)->smendx[i], i < fw->num_ids; ++i)
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struct arm_smmu_device {
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struct device *dev;
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@ -480,14 +478,16 @@ static int __find_legacy_master_phandle(struct device *dev, void *data)
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}
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static struct platform_driver arm_smmu_driver;
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static struct iommu_ops arm_smmu_ops;
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static int arm_smmu_register_legacy_master(struct device *dev)
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static int arm_smmu_register_legacy_master(struct device *dev,
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struct arm_smmu_device **smmu)
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{
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struct arm_smmu_device *smmu;
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struct arm_smmu_master_cfg *cfg;
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struct device *smmu_dev;
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struct device_node *np;
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struct of_phandle_iterator it;
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void *data = ⁢
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u32 *sids;
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__be32 pci_sid;
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int err;
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@ -500,20 +500,13 @@ static int arm_smmu_register_legacy_master(struct device *dev)
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it.node = np;
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err = driver_for_each_device(&arm_smmu_driver.driver, NULL, &data,
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__find_legacy_master_phandle);
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smmu_dev = data;
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of_node_put(np);
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if (err == 0)
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return -ENODEV;
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if (err < 0)
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return err;
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smmu = dev_get_drvdata(data);
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if (it.cur_count > MAX_MASTER_STREAMIDS) {
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dev_err(smmu->dev,
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"reached maximum number (%d) of stream IDs for master device %s\n",
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MAX_MASTER_STREAMIDS, dev_name(dev));
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return -ENOSPC;
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}
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if (dev_is_pci(dev)) {
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/* "mmu-masters" assumes Stream ID == Requester ID */
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pci_for_each_dma_alias(to_pci_dev(dev), __arm_smmu_get_pci_sid,
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@ -522,17 +515,20 @@ static int arm_smmu_register_legacy_master(struct device *dev)
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it.cur_count = 1;
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}
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cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
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if (!cfg)
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err = iommu_fwspec_init(dev, &smmu_dev->of_node->fwnode,
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&arm_smmu_ops);
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if (err)
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return err;
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sids = kcalloc(it.cur_count, sizeof(*sids), GFP_KERNEL);
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if (!sids)
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return -ENOMEM;
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cfg->smmu = smmu;
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dev->archdata.iommu = cfg;
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while (it.cur_count--)
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cfg->streamids[cfg->num_streamids++] = be32_to_cpup(it.cur++);
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return 0;
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*smmu = dev_get_drvdata(smmu_dev);
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of_phandle_iterator_args(&it, sids, it.cur_count);
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err = iommu_fwspec_add_ids(dev, sids, it.cur_count);
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kfree(sids);
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return err;
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}
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static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
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@ -1127,7 +1123,8 @@ static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx)
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static int arm_smmu_master_alloc_smes(struct device *dev)
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{
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struct arm_smmu_master_cfg *cfg = dev->archdata.iommu;
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struct iommu_fwspec *fwspec = dev->iommu_fwspec;
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struct arm_smmu_master_cfg *cfg = fwspec->iommu_priv;
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struct arm_smmu_device *smmu = cfg->smmu;
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struct arm_smmu_smr *smrs = smmu->smrs;
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struct iommu_group *group;
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@ -1135,19 +1132,19 @@ static int arm_smmu_master_alloc_smes(struct device *dev)
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mutex_lock(&smmu->stream_map_mutex);
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/* Figure out a viable stream map entry allocation */
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for_each_cfg_sme(cfg, i, idx) {
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for_each_cfg_sme(fwspec, i, idx) {
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if (idx != INVALID_SMENDX) {
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ret = -EEXIST;
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goto out_err;
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}
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ret = arm_smmu_find_sme(smmu, cfg->streamids[i], 0);
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ret = arm_smmu_find_sme(smmu, fwspec->ids[i], 0);
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if (ret < 0)
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goto out_err;
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idx = ret;
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if (smrs && smmu->s2crs[idx].count == 0) {
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smrs[idx].id = cfg->streamids[i];
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smrs[idx].id = fwspec->ids[i];
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smrs[idx].mask = 0; /* We don't currently share SMRs */
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smrs[idx].valid = true;
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}
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@ -1165,7 +1162,7 @@ static int arm_smmu_master_alloc_smes(struct device *dev)
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iommu_group_put(group);
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/* It worked! Now, poke the actual hardware */
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for_each_cfg_sme(cfg, i, idx) {
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for_each_cfg_sme(fwspec, i, idx) {
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arm_smmu_write_sme(smmu, idx);
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smmu->s2crs[idx].group = group;
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}
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@ -1182,13 +1179,14 @@ out_err:
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return ret;
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}
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static void arm_smmu_master_free_smes(struct arm_smmu_master_cfg *cfg)
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static void arm_smmu_master_free_smes(struct iommu_fwspec *fwspec)
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{
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struct arm_smmu_device *smmu = cfg->smmu;
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struct arm_smmu_device *smmu = fwspec_smmu(fwspec);
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struct arm_smmu_master_cfg *cfg = fwspec->iommu_priv;
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int i, idx;
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mutex_lock(&smmu->stream_map_mutex);
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for_each_cfg_sme(cfg, i, idx) {
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for_each_cfg_sme(fwspec, i, idx) {
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if (arm_smmu_free_sme(smmu, idx))
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arm_smmu_write_sme(smmu, idx);
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cfg->smendx[i] = INVALID_SMENDX;
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@ -1197,7 +1195,7 @@ static void arm_smmu_master_free_smes(struct arm_smmu_master_cfg *cfg)
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}
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static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_master_cfg *cfg)
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struct iommu_fwspec *fwspec)
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{
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_s2cr *s2cr = smmu->s2crs;
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@ -1214,7 +1212,7 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA)
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type = S2CR_TYPE_BYPASS;
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for_each_cfg_sme(cfg, i, idx) {
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for_each_cfg_sme(fwspec, i, idx) {
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if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)
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continue;
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@ -1229,16 +1227,18 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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{
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int ret;
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struct iommu_fwspec *fwspec = dev->iommu_fwspec;
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struct arm_smmu_device *smmu;
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struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
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struct arm_smmu_master_cfg *cfg = dev->archdata.iommu;
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if (!cfg) {
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if (!fwspec || fwspec->ops != &arm_smmu_ops) {
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dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
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return -ENXIO;
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}
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smmu = fwspec_smmu(fwspec);
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/* Ensure that the domain is finalised */
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ret = arm_smmu_init_domain_context(domain, cfg->smmu);
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ret = arm_smmu_init_domain_context(domain, smmu);
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if (ret < 0)
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return ret;
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@ -1246,15 +1246,15 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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* Sanity check the domain. We don't support domains across
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* different SMMUs.
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*/
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if (smmu_domain->smmu != cfg->smmu) {
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if (smmu_domain->smmu != smmu) {
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dev_err(dev,
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"cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
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dev_name(smmu_domain->smmu->dev), dev_name(cfg->smmu->dev));
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dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
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return -EINVAL;
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}
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/* Looks ok, so add the device to the domain */
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return arm_smmu_domain_add_master(smmu_domain, cfg);
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return arm_smmu_domain_add_master(smmu_domain, fwspec);
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}
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static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
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@ -1375,57 +1375,72 @@ static bool arm_smmu_capable(enum iommu_cap cap)
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static int arm_smmu_add_device(struct device *dev)
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{
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struct arm_smmu_device *smmu;
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struct arm_smmu_master_cfg *cfg;
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struct iommu_fwspec *fwspec;
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int i, ret;
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ret = arm_smmu_register_legacy_master(dev);
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cfg = dev->archdata.iommu;
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ret = arm_smmu_register_legacy_master(dev, &smmu);
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fwspec = dev->iommu_fwspec;
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if (ret)
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goto out_free;
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ret = -EINVAL;
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for (i = 0; i < cfg->num_streamids; i++) {
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u16 sid = cfg->streamids[i];
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for (i = 0; i < fwspec->num_ids; i++) {
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u16 sid = fwspec->ids[i];
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if (sid & ~cfg->smmu->streamid_mask) {
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if (sid & ~smmu->streamid_mask) {
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dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n",
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sid, cfg->smmu->streamid_mask);
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goto out_free;
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}
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cfg->smendx[i] = INVALID_SMENDX;
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}
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ret = -ENOMEM;
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cfg = kzalloc(offsetof(struct arm_smmu_master_cfg, smendx[i]),
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GFP_KERNEL);
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if (!cfg)
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goto out_free;
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cfg->smmu = smmu;
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fwspec->iommu_priv = cfg;
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while (i--)
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cfg->smendx[i] = INVALID_SMENDX;
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ret = arm_smmu_master_alloc_smes(dev);
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if (!ret)
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return ret;
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if (ret)
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goto out_free;
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return 0;
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out_free:
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kfree(cfg);
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dev->archdata.iommu = NULL;
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if (fwspec)
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kfree(fwspec->iommu_priv);
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iommu_fwspec_free(dev);
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return ret;
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}
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static void arm_smmu_remove_device(struct device *dev)
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{
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struct arm_smmu_master_cfg *cfg = dev->archdata.iommu;
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struct iommu_fwspec *fwspec = dev->iommu_fwspec;
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if (!cfg)
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if (!fwspec || fwspec->ops != &arm_smmu_ops)
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return;
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arm_smmu_master_free_smes(cfg);
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arm_smmu_master_free_smes(fwspec);
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iommu_group_remove_device(dev);
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kfree(cfg);
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dev->archdata.iommu = NULL;
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kfree(fwspec->iommu_priv);
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iommu_fwspec_free(dev);
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}
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static struct iommu_group *arm_smmu_device_group(struct device *dev)
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{
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struct arm_smmu_master_cfg *cfg = dev->archdata.iommu;
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struct arm_smmu_device *smmu = cfg->smmu;
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struct iommu_fwspec *fwspec = dev->iommu_fwspec;
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struct arm_smmu_device *smmu = fwspec_smmu(fwspec);
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struct iommu_group *group = NULL;
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int i, idx;
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for_each_cfg_sme(cfg, i, idx) {
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for_each_cfg_sme(fwspec, i, idx) {
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if (group && smmu->s2crs[idx].group &&
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group != smmu->s2crs[idx].group)
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return ERR_PTR(-EINVAL);
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@ -1936,6 +1951,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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}
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}
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of_iommu_set_ops(dev->of_node, &arm_smmu_ops);
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platform_set_drvdata(pdev, smmu);
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arm_smmu_device_reset(smmu);
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return 0;
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