forked from Minki/linux
sparc64: reorder functions in io_64.h
Reorder functions so __raw_{read,write}* functions comes first,
followed by {read,write}*
Update comments for the two blocks of functions.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sam Ravnborg
David S. Miller
parent
be80d844c3
commit
add79d686c
@ -12,6 +12,178 @@
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/* BIO layer definitions. */
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extern unsigned long kern_base, kern_size;
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/* __raw_{read,write}{b,w,l,q} uses direct access.
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* Access the memory as big endian bypassing the cache
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* by using ASI_PHYS_BYPASS_EC_E
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*/
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
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: /* no outputs */
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: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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/* Memory functions, same as I/O accesses on Ultra.
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* Access memory as little endian bypassing
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* the cache by using ASI_PHYS_BYPASS_EC_E_L
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*/
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#define readb readb
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static inline u8 readb(const volatile void __iomem *addr)
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{ u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readw readw
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static inline u16 readw(const volatile void __iomem *addr)
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{ u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readl readl
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static inline u32 readl(const volatile void __iomem *addr)
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{ u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readq readq
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static inline u64 readq(const volatile void __iomem *addr)
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{ u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define writeb writeb
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static inline void writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writew writew
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static inline void writew(u16 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writel writel
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static inline void writel(u32 l, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writeq writeq
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static inline void writeq(u64 q, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
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: /* no outputs */
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: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define inb inb
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static inline u8 inb(unsigned long addr)
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{
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@ -122,177 +294,11 @@ static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned l
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outsl((unsigned long __force)port, buf, count);
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}
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/* Memory functions, same as I/O accesses on Ultra. */
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#define readb readb
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static inline u8 readb(const volatile void __iomem *addr)
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{ u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readw readw
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static inline u16 readw(const volatile void __iomem *addr)
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{ u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readl readl
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static inline u32 readl(const volatile void __iomem *addr)
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{ u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readq readq
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static inline u64 readq(const volatile void __iomem *addr)
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{ u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define writeb writeb
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static inline void writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writew writew
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static inline void writew(u16 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writel writel
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static inline void writel(u32 l, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writeq writeq
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static inline void writeq(u64 q, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
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: /* no outputs */
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: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define readb_relaxed(__addr) readb(__addr)
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#define readw_relaxed(__addr) readw(__addr)
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#define readl_relaxed(__addr) readl(__addr)
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#define readq_relaxed(__addr) readq(__addr)
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/* Now versions without byte-swapping. */
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
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: /* no outputs */
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: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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/* Valid I/O Space regions are anywhere, because each PCI bus supported
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* can live in an arbitrary area of the physical address range.
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*/
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