forked from Minki/linux
Staging: comedi: fix code style errors in s626.c
A patch for s626.c to fix errors reported by checkpatch.pl tool, namely, -code indent should use tabs where possible -"foo * bar" should be "foo *bar" -trailing statements should be on next line Signed-off-by: John Sheehan <john.d.sheehan@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
John Sheehan
Greg Kroah-Hartman
parent
2fa5e380da
commit
add74595e5
@ -60,10 +60,10 @@ INSN_CONFIG instructions:
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insn.insn=INSN_CONFIG; //configuration instruction
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insn.n=1; //number of operation (must be 1)
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insn.data=&initialvalue; //initial value loaded into encoder
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//during configuration
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//during configuration
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insn.subdev=5; //encoder subdevice
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insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
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//to configure
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//to configure
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comedi_do_insn(cf,&insn); //executing configuration
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*/
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@ -299,7 +299,7 @@ static int s626_enc_insn_write(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn, unsigned int *data);
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static int s626_ns_to_timer(int *nanosec, int round_mode);
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static int s626_ai_load_polllist(uint8_t * ppl, struct comedi_cmd *cmd);
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static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd);
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static int s626_ai_inttrig(struct comedi_device *dev,
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struct comedi_subdevice *s, unsigned int trignum);
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static irqreturn_t s626_irq_handler(int irq, void *d);
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@ -330,16 +330,16 @@ static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
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/* COUNTER OBJECT ------------------------------------------------ */
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struct enc_private {
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/* Pointers to functions that differ for A and B counters: */
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uint16_t(*GetEnable) (struct comedi_device * dev, struct enc_private *); /* Return clock enable. */
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uint16_t(*GetIntSrc) (struct comedi_device * dev, struct enc_private *); /* Return interrupt source. */
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uint16_t(*GetLoadTrig) (struct comedi_device * dev, struct enc_private *); /* Return preload trigger source. */
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uint16_t(*GetMode) (struct comedi_device * dev, struct enc_private *); /* Return standardized operating mode. */
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void (*PulseIndex) (struct comedi_device * dev, struct enc_private *); /* Generate soft index strobe. */
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void (*SetEnable) (struct comedi_device * dev, struct enc_private *, uint16_t enab); /* Program clock enable. */
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void (*SetIntSrc) (struct comedi_device * dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */
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void (*SetLoadTrig) (struct comedi_device * dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */
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void (*SetMode) (struct comedi_device * dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
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void (*ResetCapFlags) (struct comedi_device * dev, struct enc_private *); /* Reset event capture flags. */
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uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *); /* Return clock enable. */
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uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *); /* Return interrupt source. */
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uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *); /* Return preload trigger source. */
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uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *); /* Return standardized operating mode. */
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void (*PulseIndex) (struct comedi_device *dev, struct enc_private *); /* Generate soft index strobe. */
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void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab); /* Program clock enable. */
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void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */
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void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */
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void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
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void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *); /* Reset event capture flags. */
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uint16_t MyCRA; /* Address of CRA register. */
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uint16_t MyCRB; /* Address of CRB register. */
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@ -815,7 +815,8 @@ static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it)
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/* Write I2C control: abort any I2C activity. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC);
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/* Invoke command upload */
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while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0) ;
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while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
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;
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/* and wait for upload to complete. */
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/* Per SAA7146 data sheet, write to STATUS reg twice to
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@ -824,7 +825,8 @@ static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it)
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WR7146(P_I2CSTAT, I2C_CLKSEL);
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/* Write I2C control: reset error flags. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
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while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ;
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while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
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;
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/* and wait for upload to complete. */
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}
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@ -1687,7 +1689,8 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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/* shift into FB BUFFER 1 register. */
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/* Wait for ADC done. */
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while (!(RR7146(P_PSR) & PSR_GPIO2)) ;
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while (!(RR7146(P_PSR) & PSR_GPIO2))
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;
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/* Fetch ADC data. */
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if (n != 0)
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@ -1719,7 +1722,8 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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/* Wait for the data to arrive in FB BUFFER 1 register. */
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/* Wait for ADC done. */
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while (!(RR7146(P_PSR) & PSR_GPIO2)) ;
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while (!(RR7146(P_PSR) & PSR_GPIO2))
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;
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/* Fetch ADC data from audio interface's input shift register. */
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@ -1732,7 +1736,7 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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return n;
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}
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static int s626_ai_load_polllist(uint8_t * ppl, struct comedi_cmd *cmd)
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static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
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{
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int n;
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@ -2461,8 +2465,7 @@ static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
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static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
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/* TrimDac LogicalChan-to-EepromAdrs mapping table. */
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static uint8_t trimadrs[] =
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{ 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
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static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
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static void LoadTrimDACs(struct comedi_device *dev)
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{
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@ -2560,10 +2563,12 @@ static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
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/* upload confirmation. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC);
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while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ;
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while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
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;
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/* Wait until I2C bus transfer is finished or an error occurs. */
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while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY) ;
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while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
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;
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/* Return non-zero if I2C error occured. */
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return RR7146(P_I2CCTRL) & I2C_ERR;
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@ -2677,7 +2682,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* Done by polling the DMAC enable flag; this flag is automatically
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* cleared when the transfer has finished.
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*/
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while ((RR7146(P_MC1) & MC1_A2OUT) != 0) ;
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while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
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;
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/* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
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@ -2694,7 +2700,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* finished transferring the DAC's data DWORD from the output FIFO
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* to the output buffer register.
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*/
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while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0) ;
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while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
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;
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/* Set up to trap execution at slot 0 when the TSL sequencer cycles
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* back to slot 0 after executing the EOS in slot 5. Also,
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@ -2730,7 +2737,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* from 0xFF to 0x00, which slot 0 causes to happen by shifting
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* out/in on SD2 the 0x00 that is always referenced by slot 5.
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*/
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while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) ;
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while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
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;
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}
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/* Either (1) we were too late setting the slot 0 trap; the TSL
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* sequencer restarted slot 0 before we could set the EOS trap flag,
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@ -2746,7 +2754,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* the next DAC write. This is detected when FB_BUFFER2 MSB changes
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* from 0x00 to 0xFF.
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*/
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while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0) ;
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while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
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;
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}
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static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage)
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@ -2785,10 +2794,12 @@ static void DEBItransfer(struct comedi_device *dev)
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/* Wait for completion of upload from shadow RAM to DEBI control */
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/* register. */
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while (!MC_TEST(P_MC2, MC2_UPLD_DEBI)) ;
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while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
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;
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/* Wait until DEBI transfer is done. */
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while (RR7146(P_PSR) & PSR_DEBI_S) ;
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while (RR7146(P_PSR) & PSR_DEBI_S)
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;
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}
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/* Write a value to a gate array register. */
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