forked from Minki/linux
drm/amdgpu: add mmhub v2 block for navi10 (v4)
mmhub is the memory controller hub for multi-media (VCN). v1: add place holder and initial functions (Ray) v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking) v3: switch to use amdgpu_gmc_pd_addr (Hawking) v4: squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
Alex Deucher
parent
770b93e9ee
commit
adc43c1b5e
@ -76,7 +76,7 @@ amdgpu-y += \
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gmc_v7_0.o \
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gmc_v8_0.o \
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gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \
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gfxhub_v2_0.o
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gfxhub_v2_0.o mmhub_v2_0.o
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# add IH block
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amdgpu-y += \
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442
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
Normal file
442
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
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@ -0,0 +1,442 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "mmhub_v2_0.h"
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#include "mmhub/mmhub_2_0_0_offset.h"
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#include "mmhub/mmhub_2_0_0_sh_mask.h"
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#include "mmhub/mmhub_2_0_0_default.h"
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#include "navi10_enum.h"
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#include "soc15_common.h"
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static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev)
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{
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uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
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WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
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lower_32_bits(value));
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WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
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upper_32_bits(value));
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}
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static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
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{
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mmhub_v2_0_init_gart_pt_regs(adev);
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WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
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(u32)(adev->gmc.gart_start >> 12));
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WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
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(u32)(adev->gmc.gart_start >> 44));
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WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
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(u32)(adev->gmc.gart_end >> 12));
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WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
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(u32)(adev->gmc.gart_end >> 44));
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}
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static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
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{
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uint64_t value;
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uint32_t tmp;
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/* Disable AGP. */
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
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/* Program the system aperture low logical page number. */
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
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adev->gmc.vram_start >> 18);
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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adev->gmc.vram_end >> 18);
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/* Set default page address. */
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value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
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adev->vm_manager.vram_base_offset;
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
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(u32)(value >> 12));
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
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(u32)(value >> 44));
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/* Program "protection fault". */
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
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(u32)(adev->dummy_page_addr >> 12));
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
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(u32)((u64)adev->dummy_page_addr >> 44));
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tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
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ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
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}
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static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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/* Setup TLB control */
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tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
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ENABLE_ADVANCED_DRIVER_MODEL, 1);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
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SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
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MTYPE, MTYPE_UC); /* UC, uncached */
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
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}
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static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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/* Setup L2 cache */
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tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
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/* XXX for emulation, Refer to closed source code.*/
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
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0);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
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tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
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tmp = mmMMVM_L2_CNTL3_DEFAULT;
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
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tmp = mmMMVM_L2_CNTL4_DEFAULT;
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
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}
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static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
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WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
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}
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static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
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{
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WREG32_SOC15(MMHUB, 0,
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mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
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0xFFFFFFFF);
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WREG32_SOC15(MMHUB, 0,
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mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
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0x0000000F);
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WREG32_SOC15(MMHUB, 0,
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mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
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WREG32_SOC15(MMHUB, 0,
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mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
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0);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
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0);
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}
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static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
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{
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int i;
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uint32_t tmp;
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for (i = 0; i <= 14; i++) {
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tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
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adev->vm_manager.num_level);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
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1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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PAGE_TABLE_BLOCK_SIZE,
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adev->vm_manager.block_size - 9);
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/* Send no-retry XNACK on fault to suppress VM fault storm. */
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tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
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RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
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lower_32_bits(adev->vm_manager.max_pfn - 1));
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WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
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upper_32_bits(adev->vm_manager.max_pfn - 1));
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}
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}
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static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
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{
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unsigned i;
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for (i = 0; i < 18; ++i) {
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WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
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2 * i, 0xffffffff);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
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2 * i, 0x1f);
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}
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}
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int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
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{
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if (amdgpu_sriov_vf(adev)) {
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/*
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* MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
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* VF copy registers so vbios post doesn't program them, for
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* SRIOV driver need to program them
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*/
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
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adev->gmc.vram_start >> 24);
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
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adev->gmc.vram_end >> 24);
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}
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/* GART Enable. */
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mmhub_v2_0_init_gart_aperture_regs(adev);
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mmhub_v2_0_init_system_aperture_regs(adev);
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mmhub_v2_0_init_tlb_regs(adev);
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mmhub_v2_0_init_cache_regs(adev);
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mmhub_v2_0_enable_system_domain(adev);
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mmhub_v2_0_disable_identity_aperture(adev);
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mmhub_v2_0_setup_vmid_config(adev);
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mmhub_v2_0_program_invalidation(adev);
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return 0;
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}
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void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
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{
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u32 tmp;
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u32 i;
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/* Disable all tables */
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for (i = 0; i < 16; i++)
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WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0);
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/* Setup TLB control */
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tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
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ENABLE_ADVANCED_DRIVER_MODEL, 0);
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WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
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/* Setup L2 cache */
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tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
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}
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/**
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* mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
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*
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* @adev: amdgpu_device pointer
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* @value: true redirects VM faults to the default page
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*/
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void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
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{
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u32 tmp;
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tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
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value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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if (!value) {
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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CRASH_ON_NO_RETRY_FAULT, 1);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
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CRASH_ON_RETRY_FAULT, 1);
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}
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
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}
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void mmhub_v2_0_init(struct amdgpu_device *adev)
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{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
|
||||
hub->ctx0_ptb_addr_hi32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
|
||||
hub->vm_inv_eng0_req =
|
||||
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
|
||||
hub->vm_inv_eng0_ack =
|
||||
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
|
||||
hub->vm_context0_cntl =
|
||||
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
|
||||
hub->vm_l2_pro_fault_status =
|
||||
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
|
||||
hub->vm_l2_pro_fault_cntl =
|
||||
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
|
||||
|
||||
}
|
||||
|
||||
static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
|
||||
bool enable)
|
||||
{
|
||||
uint32_t def, data, def1, data1;
|
||||
|
||||
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
|
||||
|
||||
def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
|
||||
|
||||
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
|
||||
data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
|
||||
|
||||
data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
|
||||
|
||||
} else {
|
||||
data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
|
||||
|
||||
data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
|
||||
}
|
||||
|
||||
if (def != data)
|
||||
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
|
||||
|
||||
if (def1 != data1)
|
||||
WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
|
||||
}
|
||||
|
||||
static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
|
||||
bool enable)
|
||||
{
|
||||
uint32_t def, data;
|
||||
|
||||
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
|
||||
|
||||
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
|
||||
data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
|
||||
else
|
||||
data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
|
||||
|
||||
if (def != data)
|
||||
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
|
||||
}
|
||||
|
||||
int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
|
||||
enum amd_clockgating_state state)
|
||||
{
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
return 0;
|
||||
|
||||
switch (adev->asic_type) {
|
||||
case CHIP_NAVI10:
|
||||
mmhub_v2_0_update_medium_grain_clock_gating(adev,
|
||||
state == AMD_CG_STATE_GATE ? true : false);
|
||||
mmhub_v2_0_update_medium_grain_light_sleep(adev,
|
||||
state == AMD_CG_STATE_GATE ? true : false);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
|
||||
{
|
||||
int data, data1;
|
||||
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
*flags = 0;
|
||||
|
||||
data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
|
||||
|
||||
data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
|
||||
|
||||
/* AMD_CG_SUPPORT_MC_MGCG */
|
||||
if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
|
||||
!(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
|
||||
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
|
||||
*flags |= AMD_CG_SUPPORT_MC_MGCG;
|
||||
|
||||
/* AMD_CG_SUPPORT_MC_LS */
|
||||
if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
|
||||
*flags |= AMD_CG_SUPPORT_MC_LS;
|
||||
}
|
||||
35
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
Normal file
35
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright 2019 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef __MMHUB_V2_0_H__
|
||||
#define __MMHUB_V2_0_H__
|
||||
|
||||
int mmhub_v2_0_gart_enable(struct amdgpu_device *adev);
|
||||
void mmhub_v2_0_gart_disable(struct amdgpu_device *adev);
|
||||
void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
|
||||
bool value);
|
||||
void mmhub_v2_0_init(struct amdgpu_device *adev);
|
||||
int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
|
||||
enum amd_clockgating_state state);
|
||||
void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user