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drm/amd/pp: Implement get_max_high_clocks for CI/VI

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v2: add table length check.

DC component expect PP to give max engine clock and
memory clock through pp_get_display_mode_validation_clocks
on DGPU as well.

This patch can fix MultiGPU-Display blank
out with 1 IGPU-4k display and 2 DGPU-two 4K
displays.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2017-11-08 16:39:00 +08:00 committed by Alex Deucher
parent d25426495f
commit ad8cec7df5
1 changed files with 20 additions and 0 deletions
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20
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
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@ -4651,6 +4651,25 @@ static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
return 0;
}
static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
struct amd_pp_simple_clock_info *clocks)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
if (clocks == NULL)
return -EINVAL;
clocks->memory_max_clock = mclk_table->count > 1 ?
mclk_table->dpm_levels[mclk_table->count-1].value :
mclk_table->dpm_levels[0].value;
clocks->engine_max_clock = sclk_table->count > 1 ?
sclk_table->dpm_levels[sclk_table->count-1].value :
sclk_table->dpm_levels[0].value;
return 0;
}
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = &smu7_hwmgr_backend_init,
.backend_fini = &smu7_hwmgr_backend_fini,
@ -4703,6 +4722,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.disable_smc_firmware_ctf = smu7_thermal_disable_alert,
.start_thermal_controller = smu7_start_thermal_controller,
.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
.get_max_high_clocks = smu7_get_max_high_clocks,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,