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drm/amd/display: Add dc_debug flag to disable min fclk

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[Why&How]
Add debug flag for an option to disable min fclk.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2020-06-24 16:26:12 -04:00 committed by Alex Deucher
parent 73affd3052
commit ad0d8ebcb8
3 changed files with 4 additions and 3 deletions
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4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
View File

@ -136,13 +136,13 @@ void vg_update_clocks(struct clk_mgr *clk_mgr_base,
} }
} }
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) {
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
} }
if (should_set_clock(safe_to_lower, if (should_set_clock(safe_to_lower,
new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) {
clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
} }

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -460,6 +460,7 @@ struct dc_debug_options {
enum pipe_split_policy pipe_split_policy; enum pipe_split_policy pipe_split_policy;
bool force_single_disp_pipe_split; bool force_single_disp_pipe_split;
bool voltage_align_fclk; bool voltage_align_fclk;
bool disable_min_fclk;
bool disable_dfs_bypass; bool disable_dfs_bypass;
bool disable_dpp_power_gate; bool disable_dpp_power_gate;

2
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright 2020 Advanced Micro Devices, Inc. * Copyright 2019-2021 Advanced Micro Devices, Inc.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),