spi: fsl-espi: add support for ESPI RXSKIP mode
This patch adds support for ESPI RXSKIP mode. This mode is optimized for flash reads: - sends a number of bytes and then reads a number of bytes - shifts out zeros automatically when reading Supporting RXSKIP mode is a prerequisite for supporting dual output read mode. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Mark Brown
parent
8f3086d2a9
commit
aca75157d9
@@ -150,7 +150,8 @@ static void fsl_espi_copy_to_buf(struct spi_message *m,
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list_for_each_entry(t, &m->transfers, transfer_list) {
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->tx_buf)
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if (t->tx_buf)
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fsl_espi_memcpy_swab(buf, t->tx_buf, m, t);
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fsl_espi_memcpy_swab(buf, t->tx_buf, m, t);
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else
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/* In RXSKIP mode controller shifts out zeros internally */
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else if (!mspi->rxskip)
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memset(buf, 0, t->len);
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memset(buf, 0, t->len);
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buf += t->len;
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buf += t->len;
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}
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}
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@@ -203,6 +204,37 @@ static int fsl_espi_check_message(struct spi_message *m)
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return 0;
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return 0;
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}
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}
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static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
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{
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struct spi_transfer *t;
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unsigned int i = 0, rxskip = 0;
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/*
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* prerequisites for ESPI rxskip mode:
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* - message has two transfers
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* - first transfer is a write and second is a read
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*
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* In addition the current low-level transfer mechanism requires
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* that the rxskip bytes fit into the TX FIFO. Else the transfer
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* would hang because after the first FSL_ESPI_FIFO_SIZE bytes
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* the TX FIFO isn't re-filled.
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*/
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (i == 0) {
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if (!t->tx_buf || t->rx_buf ||
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t->len > FSL_ESPI_FIFO_SIZE)
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return 0;
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rxskip = t->len;
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} else if (i == 1) {
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if (t->tx_buf || !t->rx_buf)
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return 0;
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}
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i++;
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}
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return i == 2 ? rxskip : 0;
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}
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static void fsl_espi_fill_tx_fifo(struct mpc8xxx_spi *mspi, u32 events)
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static void fsl_espi_fill_tx_fifo(struct mpc8xxx_spi *mspi, u32 events)
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{
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{
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u32 tx_fifo_avail;
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u32 tx_fifo_avail;
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@@ -281,7 +313,7 @@ static void fsl_espi_setup_transfer(struct spi_device *spi,
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static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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u32 mask;
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u32 mask, spcom;
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int ret;
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int ret;
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mpc8xxx_spi->rx_len = t->len;
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mpc8xxx_spi->rx_len = t->len;
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@@ -293,8 +325,18 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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reinit_completion(&mpc8xxx_spi->done);
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reinit_completion(&mpc8xxx_spi->done);
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/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
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/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM,
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spcom = SPCOM_CS(spi->chip_select);
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(SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
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spcom |= SPCOM_TRANLEN(t->len - 1);
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/* configure RXSKIP mode */
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if (mpc8xxx_spi->rxskip) {
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spcom |= SPCOM_RXSKIP(mpc8xxx_spi->rxskip);
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mpc8xxx_spi->tx_len = mpc8xxx_spi->rxskip;
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mpc8xxx_spi->rx_len = t->len - mpc8xxx_spi->rxskip;
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mpc8xxx_spi->rx = t->rx_buf + mpc8xxx_spi->rxskip;
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}
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fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, spcom);
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/* enable interrupts */
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/* enable interrupts */
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mask = SPIM_DON;
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mask = SPIM_DON;
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@@ -326,6 +368,7 @@ static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
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struct spi_device *spi = m->spi;
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struct spi_device *spi = m->spi;
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int ret;
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int ret;
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mspi->rxskip = fsl_espi_check_rxskip_mode(m);
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fsl_espi_copy_to_buf(m, mspi);
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fsl_espi_copy_to_buf(m, mspi);
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fsl_espi_setup_transfer(spi, trans);
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fsl_espi_setup_transfer(spi, trans);
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@@ -31,6 +31,7 @@ struct mpc8xxx_spi {
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#if IS_ENABLED(CONFIG_SPI_FSL_ESPI)
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#if IS_ENABLED(CONFIG_SPI_FSL_ESPI)
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unsigned int rx_len;
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unsigned int rx_len;
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unsigned int tx_len;
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unsigned int tx_len;
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unsigned int rxskip;
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u8 *local_buf;
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u8 *local_buf;
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spinlock_t lock;
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spinlock_t lock;
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#endif
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#endif
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