forked from Minki/linux
arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
We have one dual-port SATA3 AHCI controller present in NS2 SoC. This patch enables SATA3 AHCI controller and SATA3 PHY for NS2 SoC in NS2 DT. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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@ -117,6 +117,18 @@
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};
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};
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};
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};
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&sata_phy0 {
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status = "ok";
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};
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&sata_phy1 {
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status = "ok";
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};
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&sata {
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status = "ok";
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};
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&sdio0 {
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&sdio0 {
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status = "ok";
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status = "ok";
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};
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};
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@ -368,6 +368,49 @@
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reg = <0x66220000 0x28>;
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reg = <0x66220000 0x28>;
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};
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};
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sata_phy: sata_phy@663f0100 {
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compatible = "brcm,iproc-ns2-sata-phy";
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reg = <0x663f0100 0x1f00>,
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<0x663f004c 0x10>;
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reg-names = "phy", "phy-ctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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sata_phy0: sata-phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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sata_phy1: sata-phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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sata: ahci@663f2000 {
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compatible = "brcm,iproc-ahci", "generic-ahci";
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reg = <0x663f2000 0x1000>;
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reg-names = "ahci";
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interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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sata0: sata-port@0 {
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reg = <0>;
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phys = <&sata_phy0>;
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phy-names = "sata-phy";
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};
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sata1: sata-port@1 {
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reg = <1>;
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phys = <&sata_phy1>;
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phy-names = "sata-phy";
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};
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};
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sdio0: sdhci@66420000 {
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sdio0: sdhci@66420000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x66420000 0x100>;
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reg = <0x66420000 0x100>;
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