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ARM: dts: aspeed: Add PECI controller nodes

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Add PECI controller nodes with all required information.

Co-developed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Link: https://lore.kernel.org/r/20220208153639.255278-4-iwona.winiarska@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Iwona Winiarska 2022-02-08 16:36:29 +01:00 committed by Greg Kroah-Hartman
parent 0af618d68d
commit ac2743a7f6
3 changed files with 33 additions and 0 deletions
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11
arch/arm/boot/dts/aspeed-g4.dtsi
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@ -392,6 +392,17 @@
};
};
peci0: peci-controller@1e78b000 {
compatible = "aspeed,ast2400-peci";
reg = <0x1e78b000 0x60>;
interrupts = <15>;
clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
resets = <&syscon ASPEED_RESET_PECI>;
cmd-timeout-ms = <1000>;
clock-frequency = <1000000>;
status = "disabled";
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;

11
arch/arm/boot/dts/aspeed-g5.dtsi
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@ -516,6 +516,17 @@
};
};
peci0: peci-controller@1e78b000 {
compatible = "aspeed,ast2500-peci";
reg = <0x1e78b000 0x60>;
interrupts = <15>;
clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
resets = <&syscon ASPEED_RESET_PECI>;
cmd-timeout-ms = <1000>;
clock-frequency = <1000000>;
status = "disabled";
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;

11
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -512,6 +512,17 @@
status = "disabled";
};
peci0: peci-controller@1e78b000 {
compatible = "aspeed,ast2600-peci";
reg = <0x1e78b000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;
resets = <&syscon ASPEED_RESET_PECI>;
cmd-timeout-ms = <1000>;
clock-frequency = <1000000>;
status = "disabled";
};
lpc: lpc@1e789000 {
compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;