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drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll

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There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list.  We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.

Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-15-enric.balletbo@collabora.com
This commit is contained in:
zain wang 2018-04-23 12:49:50 +02:00 committed by Andrzej Hajda
parent 2a7b44c524
commit ac0c0b611d
1 changed files with 12 additions and 8 deletions
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20
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
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@ -230,16 +230,20 @@ enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
{ {
u32 reg; u32 reg;
u32 mask = DP_PLL_PD;
u32 pd_addr = ANALOGIX_DP_PLL_CTL;
if (enable) { if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); pd_addr = ANALOGIX_DP_PD;
reg |= DP_PLL_PD; mask = RK_PLL_PD;
writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
} else {
reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
reg &= ~DP_PLL_PD;
writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
} }
reg = readl(dp->reg_base + pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + pd_addr);
} }
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,