iwlwifi: always check that grab_nic_access succeeds
This allows to let sparse check that the NIC access is always released. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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c8f9b0feab
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abae2386d5
@ -354,7 +354,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
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/* Make sure device is powered up for SRAM reads */
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spin_lock_irqsave(&priv->trans->reg_lock, reg_flags);
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if (unlikely(!iwl_trans_grab_nic_access(priv->trans, false))) {
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if (!iwl_trans_grab_nic_access(priv->trans, false)) {
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spin_unlock_irqrestore(&priv->trans->reg_lock, reg_flags);
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return;
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}
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@ -1718,7 +1718,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
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/* Make sure device is powered up for SRAM reads */
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spin_lock_irqsave(&trans->reg_lock, reg_flags);
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if (unlikely(!iwl_trans_grab_nic_access(trans, false)))
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if (!iwl_trans_grab_nic_access(trans, false))
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goto out_unlock;
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/* Set starting address; reads will auto-increment */
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@ -186,7 +186,7 @@ static void iwl_tt_check_exit_ct_kill(unsigned long data)
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}
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iwl_read32(priv->trans, CSR_UCODE_DRV_GP1);
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spin_lock_irqsave(&priv->trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(priv->trans, false)))
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if (iwl_trans_grab_nic_access(priv->trans, false))
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iwl_trans_release_nic_access(priv->trans);
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spin_unlock_irqrestore(&priv->trans->reg_lock, flags);
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@ -101,13 +101,14 @@ EXPORT_SYMBOL_GPL(iwl_poll_bit);
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u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
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{
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u32 value;
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u32 value = 0x5a5a5a5a;
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_trans_grab_nic_access(trans, false);
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value = iwl_read32(trans, reg);
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iwl_trans_release_nic_access(trans);
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if (iwl_trans_grab_nic_access(trans, false)) {
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value = iwl_read32(trans, reg);
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iwl_trans_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return value;
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@ -119,7 +120,7 @@ void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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if (iwl_trans_grab_nic_access(trans, false)) {
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iwl_write32(trans, reg, value);
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iwl_trans_release_nic_access(trans);
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}
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@ -159,12 +160,13 @@ static inline void __iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
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u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
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{
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unsigned long flags;
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u32 val;
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u32 val = 0x5a5a5a5a;
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_trans_grab_nic_access(trans, false);
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val = __iwl_read_prph(trans, ofs);
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iwl_trans_release_nic_access(trans);
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if (iwl_trans_grab_nic_access(trans, false)) {
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val = __iwl_read_prph(trans, ofs);
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iwl_trans_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return val;
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}
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@ -175,7 +177,7 @@ void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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if (iwl_trans_grab_nic_access(trans, false)) {
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__iwl_write_prph(trans, ofs, val);
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iwl_trans_release_nic_access(trans);
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}
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@ -188,7 +190,7 @@ void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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if (iwl_trans_grab_nic_access(trans, false)) {
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__iwl_write_prph(trans, ofs,
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__iwl_read_prph(trans, ofs) | mask);
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iwl_trans_release_nic_access(trans);
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@ -203,7 +205,7 @@ void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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if (iwl_trans_grab_nic_access(trans, false)) {
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__iwl_write_prph(trans, ofs,
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(__iwl_read_prph(trans, ofs) & mask) | bits);
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iwl_trans_release_nic_access(trans);
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@ -218,7 +220,7 @@ void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
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u32 val;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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if (iwl_trans_grab_nic_access(trans, false)) {
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val = __iwl_read_prph(trans, ofs);
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__iwl_write_prph(trans, ofs, (val & ~mask));
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iwl_trans_release_nic_access(trans);
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@ -467,7 +467,10 @@ static int iwl_test_indirect_read(struct iwl_test *tst, u32 addr, u32 size)
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if (IWL_ABS_PRPH_START <= addr &&
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addr < IWL_ABS_PRPH_START + PRPH_END) {
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_trans_grab_nic_access(trans, false);
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if (!iwl_trans_grab_nic_access(trans, false)) {
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return -EIO;
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}
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iwl_write32(trans, HBUS_TARG_PRPH_RADDR,
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addr | (3 << 24));
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for (i = 0; i < size; i += 4)
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@ -500,26 +503,29 @@ static int iwl_test_indirect_write(struct iwl_test *tst, u32 addr,
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if (IWL_ABS_PRPH_START <= addr &&
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addr < IWL_ABS_PRPH_START + PRPH_END) {
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/* Periphery writes can be 1-3 bytes long, or DWORDs */
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if (size < 4) {
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memcpy(&val, buf, size);
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_trans_grab_nic_access(trans, false);
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iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
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(addr & 0x0000FFFF) |
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((size - 1) << 24));
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iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
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iwl_trans_release_nic_access(trans);
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/* needed after consecutive writes w/o read */
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mmiowb();
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/* Periphery writes can be 1-3 bytes long, or DWORDs */
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if (size < 4) {
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memcpy(&val, buf, size);
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (!iwl_trans_grab_nic_access(trans, false)) {
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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} else {
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if (size % 4)
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return -EINVAL;
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for (i = 0; i < size; i += 4)
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iwl_write_prph(trans, addr+i,
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*(u32 *)(buf+i));
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return -EIO;
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}
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iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
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(addr & 0x0000FFFF) |
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((size - 1) << 24));
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iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
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iwl_trans_release_nic_access(trans);
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/* needed after consecutive writes w/o read */
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mmiowb();
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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} else {
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if (size % 4)
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return -EINVAL;
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for (i = 0; i < size; i += 4)
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iwl_write_prph(trans, addr+i,
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*(u32 *)(buf+i));
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}
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} else if (iwl_test_valid_hw_addr(tst, addr)) {
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iwl_trans_write_mem(trans, addr, buf, size / 4);
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} else {
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@ -734,15 +734,15 @@ static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
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trans->ops->set_pmi(trans, state);
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}
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static inline bool iwl_trans_grab_nic_access(struct iwl_trans *trans,
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bool silent)
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{
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return trans->ops->grab_nic_access(trans, silent);
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}
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#define iwl_trans_grab_nic_access(trans, silent) \
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__cond_lock(nic_access, \
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likely((trans)->ops->grab_nic_access(trans, silent)))
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static inline void iwl_trans_release_nic_access(struct iwl_trans *trans)
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static inline void __releases(nic_access)
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iwl_trans_release_nic_access(struct iwl_trans *trans)
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{
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trans->ops->release_nic_access(trans);
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__release(nic_access);
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}
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/*****************************************************
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@ -795,7 +795,7 @@ static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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if (iwl_trans_grab_nic_access(trans, false)) {
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
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@ -815,7 +815,7 @@ static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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if (iwl_trans_grab_nic_access(trans, false)) {
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iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
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