octeontx2-af: NIX block admin queue init
Initialize NIX admin queue (AQ) i.e alloc memory for AQ instructions and for the results. All NIX LFs will submit instructions to AQ to init/write/read RQ/SQ/CQ/RSS contexts and in case of read, get context from result memory. Also before configuring/using NIX block calibrate X2P bus and check if NIX interfaces like CGX and LBK are in active and working state. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
David S. Miller
parent
57856dde11
commit
aba53d5dbc
@ -7,4 +7,4 @@ obj-$(CONFIG_OCTEONTX2_MBOX) += octeontx2_mbox.o
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obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o
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octeontx2_mbox-y := mbox.o
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octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o
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octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o
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@ -566,6 +566,7 @@ static void rvu_free_hw_resources(struct rvu *rvu)
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u64 cfg;
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rvu_npa_freemem(rvu);
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rvu_nix_freemem(rvu);
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/* Free block LF bitmaps */
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for (id = 0; id < BLK_COUNT; id++) {
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@ -774,6 +775,10 @@ init:
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if (err)
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return err;
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err = rvu_nix_init(rvu);
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if (err)
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return err;
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return 0;
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}
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@ -226,4 +226,8 @@ int rvu_mbox_handler_NPA_LF_ALLOC(struct rvu *rvu,
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struct npa_lf_alloc_rsp *rsp);
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int rvu_mbox_handler_NPA_LF_FREE(struct rvu *rvu, struct msg_req *req,
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struct msg_rsp *rsp);
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/* NIX APIs */
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int rvu_nix_init(struct rvu *rvu);
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void rvu_nix_freemem(struct rvu *rvu);
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#endif /* RVU_H */
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138
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
Normal file
138
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
Normal file
@ -0,0 +1,138 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "rvu_struct.h"
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#include "rvu_reg.h"
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#include "rvu.h"
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#include "cgx.h"
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static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr)
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{
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int idx, err;
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u64 status;
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/* Start X2P bus calibration */
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rvu_write64(rvu, blkaddr, NIX_AF_CFG,
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rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9));
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/* Wait for calibration to complete */
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err = rvu_poll_reg(rvu, blkaddr,
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NIX_AF_STATUS, BIT_ULL(10), false);
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if (err) {
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dev_err(rvu->dev, "NIX X2P bus calibration failed\n");
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return err;
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}
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status = rvu_read64(rvu, blkaddr, NIX_AF_STATUS);
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/* Check if CGX devices are ready */
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for (idx = 0; idx < cgx_get_cgx_cnt(); idx++) {
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if (status & (BIT_ULL(16 + idx)))
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continue;
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dev_err(rvu->dev,
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"CGX%d didn't respond to NIX X2P calibration\n", idx);
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err = -EBUSY;
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}
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/* Check if LBK is ready */
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if (!(status & BIT_ULL(19))) {
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dev_err(rvu->dev,
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"LBK didn't respond to NIX X2P calibration\n");
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err = -EBUSY;
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}
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/* Clear 'calibrate_x2p' bit */
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rvu_write64(rvu, blkaddr, NIX_AF_CFG,
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rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9));
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if (err || (status & 0x3FFULL))
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dev_err(rvu->dev,
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"NIX X2P calibration failed, status 0x%llx\n", status);
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if (err)
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return err;
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return 0;
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}
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static int nix_aq_init(struct rvu *rvu, struct rvu_block *block)
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{
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u64 cfg;
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int err;
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/* Set admin queue endianness */
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cfg = rvu_read64(rvu, block->addr, NIX_AF_CFG);
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#ifdef __BIG_ENDIAN
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cfg |= BIT_ULL(1);
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rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg);
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#else
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cfg &= ~BIT_ULL(1);
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rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg);
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#endif
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/* Do not bypass NDC cache */
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cfg = rvu_read64(rvu, block->addr, NIX_AF_NDC_CFG);
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cfg &= ~0x3FFEULL;
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rvu_write64(rvu, block->addr, NIX_AF_NDC_CFG, cfg);
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/* Result structure can be followed by RQ/SQ/CQ context at
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* RES + 128bytes and a write mask at RES + 256 bytes, depending on
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* operation type. Alloc sufficient result memory for all operations.
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*/
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err = rvu_aq_alloc(rvu, &block->aq,
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Q_COUNT(AQ_SIZE), sizeof(struct nix_aq_inst_s),
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ALIGN(sizeof(struct nix_aq_res_s), 128) + 256);
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if (err)
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return err;
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rvu_write64(rvu, block->addr, NIX_AF_AQ_CFG, AQ_SIZE);
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rvu_write64(rvu, block->addr,
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NIX_AF_AQ_BASE, (u64)block->aq->inst->iova);
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return 0;
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}
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int rvu_nix_init(struct rvu *rvu)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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struct rvu_block *block;
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int blkaddr, err;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
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if (blkaddr < 0)
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return 0;
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block = &hw->block[blkaddr];
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/* Calibrate X2P bus to check if CGX/LBK links are fine */
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err = nix_calibrate_x2p(rvu, blkaddr);
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if (err)
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return err;
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/* Initialize admin queue */
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err = nix_aq_init(rvu, block);
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if (err)
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return err;
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/* Restore CINT timer delay to HW reset values */
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rvu_write64(rvu, blkaddr, NIX_AF_CINT_DELAY, 0x0ULL);
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return 0;
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}
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void rvu_nix_freemem(struct rvu *rvu)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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struct rvu_block *block;
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int blkaddr;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
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if (blkaddr < 0)
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return;
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block = &hw->block[blkaddr];
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rvu_aq_free(rvu, block->aq);
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}
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@ -354,4 +354,76 @@ struct npa_pool_s {
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u64 reserved_896_959; /* W14 */
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u64 reserved_960_1023; /* W15 */
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};
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/* NIX admin queue completion status */
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enum nix_aq_comp {
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NIX_AQ_COMP_NOTDONE = 0x0,
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NIX_AQ_COMP_GOOD = 0x1,
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NIX_AQ_COMP_SWERR = 0x2,
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NIX_AQ_COMP_CTX_POISON = 0x3,
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NIX_AQ_COMP_CTX_FAULT = 0x4,
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NIX_AQ_COMP_LOCKERR = 0x5,
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NIX_AQ_COMP_SQB_ALLOC_FAIL = 0x6,
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};
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/* NIX admin queue context types */
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enum nix_aq_ctype {
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NIX_AQ_CTYPE_RQ = 0x0,
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NIX_AQ_CTYPE_SQ = 0x1,
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NIX_AQ_CTYPE_CQ = 0x2,
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NIX_AQ_CTYPE_MCE = 0x3,
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NIX_AQ_CTYPE_RSS = 0x4,
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NIX_AQ_CTYPE_DYNO = 0x5,
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};
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/* NIX admin queue instruction opcodes */
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enum nix_aq_instop {
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NIX_AQ_INSTOP_NOP = 0x0,
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NIX_AQ_INSTOP_INIT = 0x1,
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NIX_AQ_INSTOP_WRITE = 0x2,
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NIX_AQ_INSTOP_READ = 0x3,
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NIX_AQ_INSTOP_LOCK = 0x4,
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NIX_AQ_INSTOP_UNLOCK = 0x5,
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};
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/* NIX admin queue instruction structure */
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struct nix_aq_inst_s {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 doneint : 1; /* W0 */
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u64 reserved_44_62 : 19;
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u64 cindex : 20;
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u64 reserved_15_23 : 9;
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u64 lf : 7;
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u64 ctype : 4;
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u64 op : 4;
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#else
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u64 op : 4;
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u64 ctype : 4;
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u64 lf : 7;
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u64 reserved_15_23 : 9;
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u64 cindex : 20;
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u64 reserved_44_62 : 19;
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u64 doneint : 1;
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#endif
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u64 res_addr; /* W1 */
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};
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/* NIX admin queue result structure */
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struct nix_aq_res_s {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 reserved_17_63 : 47; /* W0 */
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u64 doneint : 1;
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u64 compcode : 8;
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u64 ctype : 4;
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u64 op : 4;
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#else
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u64 op : 4;
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u64 ctype : 4;
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u64 compcode : 8;
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u64 doneint : 1;
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u64 reserved_17_63 : 47;
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#endif
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u64 reserved_64_127; /* W1 */
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};
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#endif /* RVU_STRUCT_H */
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