ARM: dts: rockchip: move rk3288-veryon display settings into a separate file
The chromebook .dtsi file contains common settings for veyron Chromebooks with eDP displays. Some veyron devices with a display aren't Chromebooks (e.g. 'tiger' aka 'AOpen Chromebase Mini'), move display related bits from the chromebook .dtsi into a separate file to avoid redundant DT settings. The new file is included from the chromebook .dtsi and can be included by non-Chromebook devices with a display. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -10,6 +10,7 @@
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#include <dt-bindings/input/input.h>
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#include "rk3288-veyron.dtsi"
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#include "rk3288-veyron-analog-audio.dtsi"
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#include "rk3288-veyron-edp.dtsi"
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#include "rk3288-veyron-sdmmc.dtsi"
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/ {
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@ -18,50 +19,6 @@
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i2c20 = &i2c_tunnel;
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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default-brightness-level = <128>;
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enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl_en>;
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pwms = <&pwm0 0 1000000 0>;
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post-pwm-on-delay-ms = <10>;
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pwm-off-delay-ms = <10>;
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};
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gpio-charger {
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compatible = "gpio-charger";
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charger-type = "mains";
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@ -85,35 +42,6 @@
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};
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};
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panel: panel {
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compatible ="innolux,n116bge", "simple-panel";
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status = "okay";
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power-supply = <&vcc33_lcd>;
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backlight = <&backlight>;
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panel-timing {
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clock-frequency = <74250000>;
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hactive = <1366>;
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hfront-porch = <136>;
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hback-porch = <60>;
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hsync-len = <30>;
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hsync-active = <0>;
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vactive = <768>;
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vfront-porch = <8>;
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vback-porch = <12>;
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vsync-len = <12>;
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vsync-active = <0>;
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};
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ports {
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panel_in: port {
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panel_in_edp: endpoint {
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remote-endpoint = <&edp_out_panel>;
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};
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};
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};
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};
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/* A non-regulated voltage from power supply or battery */
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vccsys: vccsys {
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compatible = "regulator-fixed";
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@ -155,33 +83,6 @@
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};
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};
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&edp {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&edp_hpd>;
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ports {
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edp_out: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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edp_out_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_in_edp>;
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};
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};
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};
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};
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&edp_phy {
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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};
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&rk808 {
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vcc11-supply = <&vcc_5v>;
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@ -234,14 +135,6 @@
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};
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};
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&vopl {
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status = "okay";
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};
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&vopl_mmu {
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status = "okay";
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};
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&pinctrl {
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pinctrl-0 = <
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/* Common for sleep and wake, but no owners */
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@ -264,12 +157,6 @@
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&bt_dev_wake_sleep
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>;
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backlight {
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bl_en: bl-en {
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rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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buttons {
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ap_lid_int_l: ap-lid-int-l {
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rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
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124
arch/arm/boot/dts/rk3288-veyron-edp.dtsi
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124
arch/arm/boot/dts/rk3288-veyron-edp.dtsi
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@ -0,0 +1,124 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron (and derivatives) fragment for the edp displays
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*
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* Copyright 2019 Google LLC
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*/
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/ {
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backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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default-brightness-level = <128>;
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enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl_en>;
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pwms = <&pwm0 0 1000000 0>;
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post-pwm-on-delay-ms = <10>;
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pwm-off-delay-ms = <10>;
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};
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panel: panel {
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compatible ="innolux,n116bge", "simple-panel";
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status = "okay";
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power-supply = <&vcc33_lcd>;
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backlight = <&backlight>;
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panel-timing {
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clock-frequency = <74250000>;
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hactive = <1366>;
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hfront-porch = <136>;
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hback-porch = <60>;
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hsync-len = <30>;
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hsync-active = <0>;
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vactive = <768>;
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vfront-porch = <8>;
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vback-porch = <12>;
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vsync-len = <12>;
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vsync-active = <0>;
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};
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ports {
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panel_in: port {
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panel_in_edp: endpoint {
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remote-endpoint = <&edp_out_panel>;
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};
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};
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};
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};
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};
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&edp {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&edp_hpd>;
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ports {
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edp_out: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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edp_out_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_in_edp>;
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};
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};
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};
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};
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&edp_phy {
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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};
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&vopl {
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status = "okay";
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};
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&vopl_mmu {
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status = "okay";
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};
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&pinctrl {
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backlight {
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bl_en: bl-en {
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rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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