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drm/amd/display: refactor clk_resync to avoid assertion

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- not all DCE has PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE bit defined.

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tony Cheng 2017-01-16 20:37:08 -05:00 committed by Alex Deucher
parent 534db19886
commit ab7044d0d1
1 changed files with 30 additions and 27 deletions
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57
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
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@ -767,41 +767,44 @@ static void dce112_program_pixel_clk_resync(
enum dc_color_depth colordepth, enum dc_color_depth colordepth,
bool enable_ycbcr420) bool enable_ycbcr420)
{ {
REG_UPDATE(PIXCLK_RESYNC_CNTL, uint32_t deep_color_cntl = 0;
PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0); uint32_t double_rate_enable = 0;
/* /*
24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1)
30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2)
48 bit mode: TMDS clock = 2 x pixel clock (2:1) 48 bit mode: TMDS clock = 2 x pixel clock (2:1)
*/ */
if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A) if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
return; double_rate_enable = enable_ycbcr420 ? 1 : 0;
switch (colordepth) { switch (colordepth) {
case COLOR_DEPTH_888: case COLOR_DEPTH_888:
REG_UPDATE_2(PIXCLK_RESYNC_CNTL, deep_color_cntl = 0;
PHYPLLA_DCCG_DEEP_COLOR_CNTL, 0, break;
PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420); case COLOR_DEPTH_101010:
break; deep_color_cntl = 1;
case COLOR_DEPTH_101010: break;
REG_UPDATE_2(PIXCLK_RESYNC_CNTL, case COLOR_DEPTH_121212:
PHYPLLA_DCCG_DEEP_COLOR_CNTL, 1, deep_color_cntl = 2;
PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420); break;
break; case COLOR_DEPTH_161616:
case COLOR_DEPTH_121212: deep_color_cntl = 3;
REG_UPDATE_2(PIXCLK_RESYNC_CNTL, break;
PHYPLLA_DCCG_DEEP_COLOR_CNTL, 2, default:
PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420); break;
break; }
case COLOR_DEPTH_161616:
REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
PHYPLLA_DCCG_DEEP_COLOR_CNTL, 3,
PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, enable_ycbcr420);
break;
default:
break;
} }
if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
else
REG_UPDATE(PIXCLK_RESYNC_CNTL,
PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
} }
static bool dce110_program_pix_clk( static bool dce110_program_pix_clk(