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riscv: dts: microchip: icicle: re-jig fabric peripheral addresses

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When users try to add onto the reference design, they find that the
current addresses that peripherals connected to Fabric InterConnect
(FIC) 3 use are restrictive. For the v2022.09 reference design, the
peripherals have been shifted down, leaving more contiguous address
space for their custom IP/peripherals.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley 2022-09-27 12:19:19 +01:00
parent 6fc655ed49
commit ab291621a8
1 changed files with 4 additions and 4 deletions
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8
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
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@ -5,18 +5,18 @@
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
"microchip,mpfs"; "microchip,mpfs";
core_pwm0: pwm@41000000 { core_pwm0: pwm@40000000 {
compatible = "microchip,corepwm-rtl-v4"; compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x41000000 0x0 0xF0>; reg = <0x0 0x40000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>; microchip,sync-update-mask = /bits/ 32 <0>;
#pwm-cells = <2>; #pwm-cells = <2>;
clocks = <&fabric_clk3>; clocks = <&fabric_clk3>;
status = "disabled"; status = "disabled";
}; };
i2c2: i2c@44000000 { i2c2: i2c@40000200 {
compatible = "microchip,corei2c-rtl-v7"; compatible = "microchip,corei2c-rtl-v7";
reg = <0x0 0x44000000 0x0 0x1000>; reg = <0x0 0x40000200 0x0 0x1000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&fabric_clk3>; clocks = <&fabric_clk3>;