forked from Minki/linux
[PATCH] gxfb: Support flat panel timings
Support TFT panels by correctly setting up the flat panel registers [akpm@osdl.org: cleanups] Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Acked-by: James Simmons <jsimmons@infradead.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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f378819a19
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@ -16,6 +16,10 @@ int gx_line_delta(int xres, int bpp);
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extern struct geode_dc_ops gx_dc_ops;
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/* MSR that tells us if a TFT or CRT is attached */
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#define GLD_MSR_CONFIG 0xC0002001
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#define GLD_MSR_CONFIG_FMT_FP 0x01
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/* Display controller registers */
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#define DC_UNLOCK 0x00
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@ -308,6 +308,7 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i
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struct geodefb_par *par;
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struct fb_info *info;
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int ret;
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unsigned long val;
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info = gxfb_init_fbinfo(&pdev->dev);
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if (!info)
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@ -323,6 +324,15 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i
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goto err;
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}
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/* Figure out if this is a TFT or CRT part */
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rdmsrl(GLD_MSR_CONFIG, val);
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if (val & GLD_MSR_CONFIG_FMT_FP)
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par->enable_crt = 0;
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else
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par->enable_crt = 1;
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ret = fb_find_mode(&info->var, info, mode_option,
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gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
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if (ret == 0 || ret == 4) {
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@ -175,10 +175,62 @@ static void gx_set_dclk_frequency(struct fb_info *info)
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} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
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}
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static void
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gx_configure_tft(struct fb_info *info)
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{
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struct geodefb_par *par = info->par;
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unsigned long val;
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unsigned long fp;
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/* Set up the DF pad select MSR */
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rdmsrl(GX_VP_MSR_PAD_SELECT, val);
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val &= ~GX_VP_PAD_SELECT_MASK;
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val |= GX_VP_PAD_SELECT_TFT;
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wrmsrl(GX_VP_MSR_PAD_SELECT, val);
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/* Turn off the panel */
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fp = readl(par->vid_regs + GX_FP_PM);
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fp &= ~GX_FP_PM_P;
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writel(fp, par->vid_regs + GX_FP_PM);
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/* Set timing 1 */
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fp = readl(par->vid_regs + GX_FP_PT1);
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fp &= GX_FP_PT1_VSIZE_MASK;
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fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT;
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writel(fp, par->vid_regs + GX_FP_PT1);
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/* Timing 2 */
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/* Set bits that are always on for TFT */
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fp = 0x0F100000;
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/* Add sync polarity */
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if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
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fp |= GX_FP_PT2_VSP;
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if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
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fp |= GX_FP_PT2_HSP;
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writel(fp, par->vid_regs + GX_FP_PT2);
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/* Set the dither control */
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writel(0x70, par->vid_regs + GX_FP_DFC);
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/* Turn on the device */
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fp = readl(par->vid_regs + GX_FP_PM);
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fp |= GX_FP_PM_P;
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writel(fp, par->vid_regs + GX_FP_PM);
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}
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static void gx_configure_display(struct fb_info *info)
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{
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struct geodefb_par *par = info->par;
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u32 dcfg, fp_pm, misc;
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u32 dcfg, misc;
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/* Set up the MISC register */
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@ -222,11 +274,10 @@ static void gx_configure_display(struct fb_info *info)
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writel(dcfg, par->vid_regs + GX_DCFG);
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/* Power on flat panel. */
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/* Set up the flat panel (if it is enabled) */
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fp_pm = readl(par->vid_regs + GX_FP_PM);
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fp_pm |= GX_FP_PM_P;
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writel(fp_pm, par->vid_regs + GX_FP_PM);
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if (par->enable_crt == 0)
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gx_configure_tft(info);
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}
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static int gx_blank_display(struct fb_info *info, int blank_mode)
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@ -267,12 +318,15 @@ static int gx_blank_display(struct fb_info *info, int blank_mode)
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writel(dcfg, par->vid_regs + GX_DCFG);
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/* Power on/off flat panel. */
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if (par->enable_crt == 0) {
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fp_pm = readl(par->vid_regs + GX_FP_PM);
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if (blank_mode == FB_BLANK_POWERDOWN)
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fp_pm &= ~GX_FP_PM_P;
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else
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fp_pm |= GX_FP_PM_P;
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writel(fp_pm, par->vid_regs + GX_FP_PM);
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}
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return 0;
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}
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@ -13,6 +13,11 @@
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extern struct geode_vid_ops gx_vid_ops;
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/* GX Flatpanel control MSR */
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#define GX_VP_MSR_PAD_SELECT 0x2011
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#define GX_VP_PAD_SELECT_MASK 0x3FFFFFFF
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#define GX_VP_PAD_SELECT_TFT 0x1FFFFFFF
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/* Geode GX video processor registers */
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#define GX_DCFG 0x0008
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@ -36,9 +41,20 @@ extern struct geode_vid_ops gx_vid_ops;
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#define GX_MISC_A_PWRDN 0x00000800
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/* Geode GX flat panel display control registers */
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#define GX_FP_PT1 0x0400
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#define GX_FP_PT1_VSIZE_MASK 0x7FF0000
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#define GX_FP_PT1_VSIZE_SHIFT 16
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#define GX_FP_PT2 0x408
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#define GX_FP_PT2_VSP (1 << 23)
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#define GX_FP_PT2_HSP (1 << 22)
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#define GX_FP_PM 0x410
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# define GX_FP_PM_P 0x01000000
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#define GX_FP_DFC 0x418
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/* Geode GX clock control MSRs */
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#define MSR_GLCP_SYS_RSTPLL 0x4c000014
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