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Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

Browse Source 
Pull media updates from Mauro Carvalho Chehab:
 - some V4L2 API updates needed by embedded devices
 - DVB API extensions for ATSC-MH delivery system, used in US for mobile
   TV
 - new tuners for fc0011/0012/0013 and tua9001
 - a new dvb driver for af9033/9035
 - a new ATSC-MH frontend (lg2160)
 - new remote controller keymaps
 - Removal of a few legacy webcam driver that got replaced by gspca on
   several kernel versions ago
 - a new driver for Exynos 4/5 webcams(s5pp fimc-lite)
 - a new webcam sensor driver (smiapp)
 - a new video input driver for embedded (sta2x1xx)
 - several improvements, fixes, cleanups, etc inside the drivers.

Manually fix up conflicts due to err() -> dev_err() conversion in
drivers/staging/media/easycap/easycap_main.c

* 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (484 commits)
  [media] saa7134-cards: Remove a PCI entry added by mistake
  [media] radio-sf16fmi: add support for SF16-FMD
  [media] rc-loopback: remove duplicate line
  [media] patch for Asus My Cinema PS3-100 (1043:48cd)
  [media] au0828: Move the Kconfig knob under V4L_USB_DRIVERS
  [media] em28xx: simple comment fix
  [media] [resend] radio-sf16fmr2: add PnP support for SF16-FMD2
  [media] smiapp: Use v4l2_ctrl_new_int_menu() instead of v4l2_ctrl_new_custom()
  [media] smiapp: Add support for 8-bit uncompressed formats
  [media] smiapp: Allow generic quirk registers
  [media] smiapp: Use non-binning limits if the binning limit is zero
  [media] smiapp: Initialise rval in smiapp_read_nvm()
  [media] smiapp: Round minimum pre_pll up rather than down in ip_clk_freq check
  [media] smiapp: Use 8-bit reads only before identifying the sensor
  [media] smiapp: Quirk for sensors that only do 8-bit reads
  [media] smiapp: Pass struct sensor to register writing commands instead of i2c_client
  [media] smiapp: Allow using external clock from the clock framework
  [media] zl10353: change .read_snr() to report SNR as a 0.1 dB
  [media] media: add support to gspca/pac7302.c for 093a:2627 (Genius FaceCam 300)
  [media] m88rs2000 - only flip bit 2 on reg 0x70 on 16th try
  ...
This commit is contained in:
Linus Torvalds
2012-05-24 10:21:51 -07:00
parent f9369910a6 71006fb22b
commit ab11ca34ee
463 changed files with 39311 additions and 16893 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
include/linux/Kbuild
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@@ -383,6 +383,7 @@ header-y += utime.h
header-y += utsname.h
header-y += uuid.h
header-y += uvcvideo.h
header-y += v4l2-dv-timings.h
header-y += v4l2-mediabus.h
header-y += v4l2-subdev.h
header-y += veth.h

51
include/linux/dvb/frontend.h
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@@ -320,7 +320,24 @@ struct dvb_frontend_event {
#define DTV_ENUM_DELSYS 44
#define DTV_MAX_COMMAND DTV_ENUM_DELSYS
/* ATSC-MH */
#define DTV_ATSCMH_FIC_VER 45
#define DTV_ATSCMH_PARADE_ID 46
#define DTV_ATSCMH_NOG 47
#define DTV_ATSCMH_TNOG 48
#define DTV_ATSCMH_SGN 49
#define DTV_ATSCMH_PRC 50
#define DTV_ATSCMH_RS_FRAME_MODE 51
#define DTV_ATSCMH_RS_FRAME_ENSEMBLE 52
#define DTV_ATSCMH_RS_CODE_MODE_PRI 53
#define DTV_ATSCMH_RS_CODE_MODE_SEC 54
#define DTV_ATSCMH_SCCC_BLOCK_MODE 55
#define DTV_ATSCMH_SCCC_CODE_MODE_A 56
#define DTV_ATSCMH_SCCC_CODE_MODE_B 57
#define DTV_ATSCMH_SCCC_CODE_MODE_C 58
#define DTV_ATSCMH_SCCC_CODE_MODE_D 59
#define DTV_MAX_COMMAND DTV_ATSCMH_SCCC_CODE_MODE_D
typedef enum fe_pilot {
PILOT_ON,
@@ -360,6 +377,38 @@ typedef enum fe_delivery_system {
#define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A
/* ATSC-MH */
enum atscmh_sccc_block_mode {
ATSCMH_SCCC_BLK_SEP = 0,
ATSCMH_SCCC_BLK_COMB = 1,
ATSCMH_SCCC_BLK_RES = 2,
};
enum atscmh_sccc_code_mode {
ATSCMH_SCCC_CODE_HLF = 0,
ATSCMH_SCCC_CODE_QTR = 1,
ATSCMH_SCCC_CODE_RES = 2,
};
enum atscmh_rs_frame_ensemble {
ATSCMH_RSFRAME_ENS_PRI = 0,
ATSCMH_RSFRAME_ENS_SEC = 1,
};
enum atscmh_rs_frame_mode {
ATSCMH_RSFRAME_PRI_ONLY = 0,
ATSCMH_RSFRAME_PRI_SEC = 1,
ATSCMH_RSFRAME_RES = 2,
};
enum atscmh_rs_code_mode {
ATSCMH_RSCODE_211_187 = 0,
ATSCMH_RSCODE_223_187 = 1,
ATSCMH_RSCODE_235_187 = 2,
ATSCMH_RSCODE_RES = 3,
};
struct dtv_cmds_h {
char *name; /* A display name for debugging purposes */

2
include/linux/dvb/version.h
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@@ -24,6 +24,6 @@
#define _DVBVERSION_H_
#define DVB_API_VERSION 5
#define DVB_API_VERSION_MINOR 5
#define DVB_API_VERSION_MINOR 6
#endif /*_DVBVERSION_H_*/

87
include/linux/fixp-arith.h Normal file
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@@ -0,0 +1,87 @@
#ifndef _FIXP_ARITH_H
#define _FIXP_ARITH_H
/*
* Simplistic fixed-point arithmetics.
* Hmm, I'm probably duplicating some code :(
*
* Copyright (c) 2002 Johann Deneux
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Should you need to contact me, the author, you can do so by
* e-mail - mail your message to <johann.deneux@gmail.com>
*/
#include <linux/types.h>
/* The type representing fixed-point values */
typedef s16 fixp_t;
#define FRAC_N 8
#define FRAC_MASK ((1<<FRAC_N)-1)
/* Not to be used directly. Use fixp_{cos,sin} */
static const fixp_t cos_table[46] = {
0x0100, 0x00FF, 0x00FF, 0x00FE, 0x00FD, 0x00FC, 0x00FA, 0x00F8,
0x00F6, 0x00F3, 0x00F0, 0x00ED, 0x00E9, 0x00E6, 0x00E2, 0x00DD,
0x00D9, 0x00D4, 0x00CF, 0x00C9, 0x00C4, 0x00BE, 0x00B8, 0x00B1,
0x00AB, 0x00A4, 0x009D, 0x0096, 0x008F, 0x0087, 0x0080, 0x0078,
0x0070, 0x0068, 0x005F, 0x0057, 0x004F, 0x0046, 0x003D, 0x0035,
0x002C, 0x0023, 0x001A, 0x0011, 0x0008, 0x0000
};
/* a: 123 -> 123.0 */
static inline fixp_t fixp_new(s16 a)
{
return a<<FRAC_N;
}
/* a: 0xFFFF -> -1.0
0x8000 -> 1.0
0x0000 -> 0.0
*/
static inline fixp_t fixp_new16(s16 a)
{
return ((s32)a)>>(16-FRAC_N);
}
static inline fixp_t fixp_cos(unsigned int degrees)
{
int quadrant = (degrees / 90) & 3;
unsigned int i = degrees % 90;
if (quadrant == 1 || quadrant == 3)
i = 90 - i;
i >>= 1;
return (quadrant == 1 || quadrant == 2)? -cos_table[i] : cos_table[i];
}
static inline fixp_t fixp_sin(unsigned int degrees)
{
return -fixp_cos(degrees + 90);
}
static inline fixp_t fixp_mult(fixp_t a, fixp_t b)
{
return ((s32)(a*b))>>FRAC_N;
}
#endif

816
include/linux/v4l2-dv-timings.h Normal file
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@@ -0,0 +1,816 @@
/*
* V4L2 DV timings header.
*
* Copyright (C) 2012 Hans Verkuil <hans.verkuil@cisco.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef _V4L2_DV_TIMINGS_H
#define _V4L2_DV_TIMINGS_H
#if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
/* Sadly gcc versions older than 4.6 have a bug in how they initialize
anonymous unions where they require additional curly brackets.
This violates the C1x standard. This workaround adds the curly brackets
if needed. */
#define V4L2_INIT_BT_TIMINGS(_width, args...) \
{ .bt = { _width , ## args } }
#else
#define V4L2_INIT_BT_TIMINGS(_width, args...) \
.bt = { _width , ## args }
#endif
/* CEA-861-E timings (i.e. standard HDTV timings) */
#define V4L2_DV_BT_CEA_640X480P59_94 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
}
#define V4L2_DV_BT_CEA_720X480P59_94 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, 0) \
}
#define V4L2_DV_BT_CEA_720X576P50 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, 0) \
}
#define V4L2_DV_BT_CEA_1280X720P24 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS) \
}
#define V4L2_DV_BT_CEA_1280X720P25 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, 0) \
}
#define V4L2_DV_BT_CEA_1280X720P30 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
}
#define V4L2_DV_BT_CEA_1280X720P50 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, 0) \
}
#define V4L2_DV_BT_CEA_1280X720P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
}
#define V4L2_DV_BT_CEA_1920X1080P24 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
}
#define V4L2_DV_BT_CEA_1920X1080P25 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, 0) \
}
#define V4L2_DV_BT_CEA_1920X1080P30 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
}
#define V4L2_DV_BT_CEA_1920X1080I50 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
}
#define V4L2_DV_BT_CEA_1920X1080P50 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
V4L2_DV_BT_STD_CEA861, 0) \
}
#define V4L2_DV_BT_CEA_1920X1080I60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
}
#define V4L2_DV_BT_CEA_1920X1080P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
V4L2_DV_FL_CAN_REDUCE_FPS) \
}
/* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
#define V4L2_DV_BT_DMT_640X350P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_640X400P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_720X400P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
/* VGA resolutions */
#define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
#define V4L2_DV_BT_DMT_640X480P72 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_640X480P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_640X480P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
/* SVGA resolutions */
#define V4L2_DV_BT_DMT_800X600P56 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(800, 600, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_800X600P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(800, 600, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_800X600P72 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(800, 600, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_800X600P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(800, 600, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_800X600P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(800, 600, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_800X600P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_848X480P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(848, 480, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1024X768I43 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
V4L2_DV_BT_STD_DMT, 0) \
}
/* XGA resolutions */
#define V4L2_DV_BT_DMT_1024X768P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1024X768P70 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1024X768P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1024X768P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1024X768P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
/* XGA+ resolution */
#define V4L2_DV_BT_DMT_1152X864P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
/* WXGA resolutions */
#define V4L2_DV_BT_DMT_1280X768P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1280X768P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1280X768P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1280X768P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1280X768P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1280X800P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1280X800P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1280X800P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1280X800P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1280X800P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1280X960P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1280X960P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1280X960P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
/* SXGA resolutions */
#define V4L2_DV_BT_DMT_1280X1024P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1280X1024P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1280X1024P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1280X1024P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1360X768P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1360X768P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1366X768P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1366X768P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
}
/* SXGA+ resolutions */
#define V4L2_DV_BT_DMT_1400X1050P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1400X1050P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1400X1050P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1400X1050P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1400X1050P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
/* WXGA+ resolutions */
#define V4L2_DV_BT_DMT_1440X900P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1440X900P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1440X900P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1440X900P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1440X900P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1600X900P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
}
/* UXGA resolutions */
#define V4L2_DV_BT_DMT_1600X1200P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1600X1200P65 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1600X1200P70 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1600X1200P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1600X1200P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1600X1200P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
/* WSXGA+ resolutions */
#define V4L2_DV_BT_DMT_1680X1050P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1680X1050P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1680X1050P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1680X1050P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1680X1050P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1792X1344P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1792X1344P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1792X1344P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1856X1392P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1856X1392P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1856X1392P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
/* WUXGA resolutions */
#define V4L2_DV_BT_DMT_1920X1200P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1920X1200P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1920X1200P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1920X1200P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_1920X1200P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1920X1440P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1920X1440P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#define V4L2_DV_BT_DMT_1920X1440P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_2048X1152P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
}
/* WQXGA resolutions */
#define V4L2_DV_BT_DMT_2560X1600P60_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_2560X1600P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_2560X1600P75 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_2560X1600P85 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
}
#define V4L2_DV_BT_DMT_2560X1600P120_RB { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_FL_REDUCED_BLANKING) \
}
#define V4L2_DV_BT_DMT_1366X768P60 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
V4L2_DV_BT_STD_DMT, 0) \
}
#endif

41
include/linux/v4l2-subdev.h
View File

@@ -123,6 +123,43 @@ struct v4l2_subdev_frame_interval_enum {
__u32 reserved[9];
};
#define V4L2_SUBDEV_SEL_FLAG_SIZE_GE (1 << 0)
#define V4L2_SUBDEV_SEL_FLAG_SIZE_LE (1 << 1)
#define V4L2_SUBDEV_SEL_FLAG_KEEP_CONFIG (1 << 2)
/* active cropping area */
#define V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL 0x0000
/* cropping bounds */
#define V4L2_SUBDEV_SEL_TGT_CROP_BOUNDS 0x0002
/* current composing area */
#define V4L2_SUBDEV_SEL_TGT_COMPOSE_ACTUAL 0x0100
/* composing bounds */
#define V4L2_SUBDEV_SEL_TGT_COMPOSE_BOUNDS 0x0102
/**
* struct v4l2_subdev_selection - selection info
*
* @which: either V4L2_SUBDEV_FORMAT_ACTIVE or V4L2_SUBDEV_FORMAT_TRY
* @pad: pad number, as reported by the media API
* @target: selection target, used to choose one of possible rectangles
* @flags: constraint flags
* @r: coordinates of the selection window
* @reserved: for future use, set to zero for now
*
* Hardware may use multiple helper windows to process a video stream.
* The structure is used to exchange this selection areas between
* an application and a driver.
*/
struct v4l2_subdev_selection {
__u32 which;
__u32 pad;
__u32 target;
__u32 flags;
struct v4l2_rect r;
__u32 reserved[8];
};
#define VIDIOC_SUBDEV_G_FMT _IOWR('V', 4, struct v4l2_subdev_format)
#define VIDIOC_SUBDEV_S_FMT _IOWR('V', 5, struct v4l2_subdev_format)
#define VIDIOC_SUBDEV_G_FRAME_INTERVAL \
@@ -137,5 +174,9 @@ struct v4l2_subdev_frame_interval_enum {
_IOWR('V', 75, struct v4l2_subdev_frame_interval_enum)
#define VIDIOC_SUBDEV_G_CROP _IOWR('V', 59, struct v4l2_subdev_crop)
#define VIDIOC_SUBDEV_S_CROP _IOWR('V', 60, struct v4l2_subdev_crop)
#define VIDIOC_SUBDEV_G_SELECTION \
_IOWR('V', 61, struct v4l2_subdev_selection)
#define VIDIOC_SUBDEV_S_SELECTION \
_IOWR('V', 62, struct v4l2_subdev_selection)
#endif

370
include/linux/videodev2.h
View File

@@ -292,10 +292,10 @@ struct v4l2_pix_format {
__u32 width;
__u32 height;
__u32 pixelformat;
enum v4l2_field field;
__u32 field; /* enum v4l2_field */
__u32 bytesperline; /* for padding, zero if unused */
__u32 sizeimage;
enum v4l2_colorspace colorspace;
__u32 colorspace; /* enum v4l2_colorspace */
__u32 priv; /* private data, depends on pixelformat */
};
@@ -378,7 +378,10 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */
#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */
/* 10bit raw bayer DPCM compressed to 8 bits */
#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8')
#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8')
#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0')
#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8')
/*
* 10bit raw bayer, expanded to 16 bits
* xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb...
@@ -432,7 +435,7 @@ struct v4l2_pix_format {
*/
struct v4l2_fmtdesc {
__u32 index; /* Format number */
enum v4l2_buf_type type; /* buffer type */
__u32 type; /* enum v4l2_buf_type */
__u32 flags;
__u8 description[32]; /* Description string */
__u32 pixelformat; /* Format fourcc */
@@ -573,8 +576,8 @@ struct v4l2_jpegcompression {
*/
struct v4l2_requestbuffers {
__u32 count;
enum v4l2_buf_type type;
enum v4l2_memory memory;
__u32 type; /* enum v4l2_buf_type */
__u32 memory; /* enum v4l2_memory */
__u32 reserved[2];
};
@@ -610,15 +613,17 @@ struct v4l2_plane {
/**
* struct v4l2_buffer - video buffer info
* @index: id number of the buffer
* @type: buffer type (type == *_MPLANE for multiplanar buffers)
* @type: enum v4l2_buf_type; buffer type (type == *_MPLANE for
* multiplanar buffers);
* @bytesused: number of bytes occupied by data in the buffer (payload);
* unused (set to 0) for multiplanar buffers
* @flags: buffer informational flags
* @field: field order of the image in the buffer
* @field: enum v4l2_field; field order of the image in the buffer
* @timestamp: frame timestamp
* @timecode: frame timecode
* @sequence: sequence count of this frame
* @memory: the method, in which the actual video data is passed
* @memory: enum v4l2_memory; the method, in which the actual video data is
* passed
* @offset: for non-multiplanar buffers with memory == V4L2_MEMORY_MMAP;
* offset from the start of the device memory for this plane,
* (or a "cookie" that should be passed to mmap() as offset)
@@ -636,16 +641,16 @@ struct v4l2_plane {
*/
struct v4l2_buffer {
__u32 index;
enum v4l2_buf_type type;
__u32 type;
__u32 bytesused;
__u32 flags;
enum v4l2_field field;
__u32 field;
struct timeval timestamp;
struct v4l2_timecode timecode;
__u32 sequence;
/* memory location */
enum v4l2_memory memory;
__u32 memory;
union {
__u32 offset;
unsigned long userptr;
@@ -708,7 +713,7 @@ struct v4l2_clip {
struct v4l2_window {
struct v4l2_rect w;
enum v4l2_field field;
__u32 field; /* enum v4l2_field */
__u32 chromakey;
struct v4l2_clip __user *clips;
__u32 clipcount;
@@ -745,14 +750,14 @@ struct v4l2_outputparm {
* I N P U T I M A G E C R O P P I N G
*/
struct v4l2_cropcap {
enum v4l2_buf_type type;
__u32 type; /* enum v4l2_buf_type */
struct v4l2_rect bounds;
struct v4l2_rect defrect;
struct v4l2_fract pixelaspect;
};
struct v4l2_crop {
enum v4l2_buf_type type;
__u32 type; /* enum v4l2_buf_type */
struct v4l2_rect c;
};
@@ -939,6 +944,9 @@ struct v4l2_standard {
__u32 reserved[4];
};
/* The DV Preset API is deprecated in favor of the DV Timings API.
New drivers shouldn't use this anymore! */
/*
* V I D E O T I M I N G S D V P R E S E T
*/
@@ -986,29 +994,56 @@ struct v4l2_dv_enum_preset {
* D V B T T I M I N G S
*/
/* BT.656/BT.1120 timing data */
/** struct v4l2_bt_timings - BT.656/BT.1120 timing data
* @width: total width of the active video in pixels
* @height: total height of the active video in lines
* @interlaced: Interlaced or progressive
* @polarities: Positive or negative polarities
* @pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000
* @hfrontporch:Horizontal front porch in pixels
* @hsync: Horizontal Sync length in pixels
* @hbackporch: Horizontal back porch in pixels
* @vfrontporch:Vertical front porch in lines
* @vsync: Vertical Sync length in lines
* @vbackporch: Vertical back porch in lines
* @il_vfrontporch:Vertical front porch for the even field
* (aka field 2) of interlaced field formats
* @il_vsync: Vertical Sync length for the even field
* (aka field 2) of interlaced field formats
* @il_vbackporch:Vertical back porch for the even field
* (aka field 2) of interlaced field formats
* @standards: Standards the timing belongs to
* @flags: Flags
* @reserved: Reserved fields, must be zeroed.
*
* A note regarding vertical interlaced timings: height refers to the total
* height of the active video frame (= two fields). The blanking timings refer
* to the blanking of each field. So the height of the total frame is
* calculated as follows:
*
* tot_height = height + vfrontporch + vsync + vbackporch +
* il_vfrontporch + il_vsync + il_vbackporch
*
* The active height of each field is height / 2.
*/
struct v4l2_bt_timings {
__u32 width; /* width in pixels */
__u32 height; /* height in lines */
__u32 interlaced; /* Interlaced or progressive */
__u32 polarities; /* Positive or negative polarity */
__u64 pixelclock; /* Pixel clock in HZ. Ex. 74.25MHz->74250000 */
__u32 hfrontporch; /* Horizpontal front porch in pixels */
__u32 hsync; /* Horizontal Sync length in pixels */
__u32 hbackporch; /* Horizontal back porch in pixels */
__u32 vfrontporch; /* Vertical front porch in pixels */
__u32 vsync; /* Vertical Sync length in lines */
__u32 vbackporch; /* Vertical back porch in lines */
__u32 il_vfrontporch; /* Vertical front porch for bottom field of
* interlaced field formats
*/
__u32 il_vsync; /* Vertical sync length for bottom field of
* interlaced field formats
*/
__u32 il_vbackporch; /* Vertical back porch for bottom field of
* interlaced field formats
*/
__u32 reserved[16];
__u32 width;
__u32 height;
__u32 interlaced;
__u32 polarities;
__u64 pixelclock;
__u32 hfrontporch;
__u32 hsync;
__u32 hbackporch;
__u32 vfrontporch;
__u32 vsync;
__u32 vbackporch;
__u32 il_vfrontporch;
__u32 il_vsync;
__u32 il_vbackporch;
__u32 standards;
__u32 flags;
__u32 reserved[14];
} __attribute__ ((packed));
/* Interlaced or progressive format */
@@ -1019,8 +1054,42 @@ struct v4l2_bt_timings {
#define V4L2_DV_VSYNC_POS_POL 0x00000001
#define V4L2_DV_HSYNC_POS_POL 0x00000002
/* Timings standards */
#define V4L2_DV_BT_STD_CEA861 (1 << 0) /* CEA-861 Digital TV Profile */
#define V4L2_DV_BT_STD_DMT (1 << 1) /* VESA Discrete Monitor Timings */
#define V4L2_DV_BT_STD_CVT (1 << 2) /* VESA Coordinated Video Timings */
#define V4L2_DV_BT_STD_GTF (1 << 3) /* VESA Generalized Timings Formula */
/* DV timings */
/* Flags */
/* CVT/GTF specific: timing uses reduced blanking (CVT) or the 'Secondary
GTF' curve (GTF). In both cases the horizontal and/or vertical blanking
intervals are reduced, allowing a higher resolution over the same
bandwidth. This is a read-only flag. */
#define V4L2_DV_FL_REDUCED_BLANKING (1 << 0)
/* CEA-861 specific: set for CEA-861 formats with a framerate of a multiple
of six. These formats can be optionally played at 1 / 1.001 speed.
This is a read-only flag. */
#define V4L2_DV_FL_CAN_REDUCE_FPS (1 << 1)
/* CEA-861 specific: only valid for video transmitters, the flag is cleared
by receivers.
If the framerate of the format is a multiple of six, then the pixelclock
used to set up the transmitter is divided by 1.001 to make it compatible
with 60 Hz based standards such as NTSC and PAL-M that use a framerate of
29.97 Hz. Otherwise this flag is cleared. If the transmitter can't generate
such frequencies, then the flag will also be cleared. */
#define V4L2_DV_FL_REDUCED_FPS (1 << 2)
/* Specific to interlaced formats: if set, then field 1 is really one half-line
longer and field 2 is really one half-line shorter, so each field has
exactly the same number of half-lines. Whether half-lines can be detected
or used depends on the hardware. */
#define V4L2_DV_FL_HALF_LINE (1 << 0)
/** struct v4l2_dv_timings - DV timings
* @type: the type of the timings
* @bt: BT656/1120 timings
*/
struct v4l2_dv_timings {
__u32 type;
union {
@@ -1032,6 +1101,64 @@ struct v4l2_dv_timings {
/* Values for the type field */
#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */
/** struct v4l2_enum_dv_timings - DV timings enumeration
* @index: enumeration index
* @reserved: must be zeroed
* @timings: the timings for the given index
*/
struct v4l2_enum_dv_timings {
__u32 index;
__u32 reserved[3];
struct v4l2_dv_timings timings;
};
/** struct v4l2_bt_timings_cap - BT.656/BT.1120 timing capabilities
* @min_width: width in pixels
* @max_width: width in pixels
* @min_height: height in lines
* @max_height: height in lines
* @min_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000
* @max_pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000
* @standards: Supported standards
* @capabilities: Supported capabilities
* @reserved: Must be zeroed
*/
struct v4l2_bt_timings_cap {
__u32 min_width;
__u32 max_width;
__u32 min_height;
__u32 max_height;
__u64 min_pixelclock;
__u64 max_pixelclock;
__u32 standards;
__u32 capabilities;
__u32 reserved[16];
} __attribute__ ((packed));
/* Supports interlaced formats */
#define V4L2_DV_BT_CAP_INTERLACED (1 << 0)
/* Supports progressive formats */
#define V4L2_DV_BT_CAP_PROGRESSIVE (1 << 1)
/* Supports CVT/GTF reduced blanking */
#define V4L2_DV_BT_CAP_REDUCED_BLANKING (1 << 2)
/* Supports custom formats */
#define V4L2_DV_BT_CAP_CUSTOM (1 << 3)
/** struct v4l2_dv_timings_cap - DV timings capabilities
* @type: the type of the timings (same as in struct v4l2_dv_timings)
* @bt: the BT656/1120 timings capabilities
*/
struct v4l2_dv_timings_cap {
__u32 type;
__u32 reserved[3];
union {
struct v4l2_bt_timings_cap bt;
__u32 raw_data[32];
};
};
/*
* V I D E O I N P U T S
*/
@@ -1040,7 +1167,7 @@ struct v4l2_input {
__u8 name[32]; /* Label */
__u32 type; /* Type of input */
__u32 audioset; /* Associated audios (bitfield) */
__u32 tuner; /* Associated tuner */
__u32 tuner; /* enum v4l2_tuner_type */
v4l2_std_id std;
__u32 status;
__u32 capabilities;
@@ -1137,6 +1264,8 @@ struct v4l2_ext_controls {
#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator control class */
#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */
#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */
#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 /* Image source controls */
#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 /* Image processing controls */
#define V4L2_CTRL_ID_MASK (0x0fffffff)
#define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL)
@@ -1151,12 +1280,13 @@ enum v4l2_ctrl_type {
V4L2_CTRL_TYPE_CTRL_CLASS = 6,
V4L2_CTRL_TYPE_STRING = 7,
V4L2_CTRL_TYPE_BITMASK = 8,
V4L2_CTRL_TYPE_INTEGER_MENU = 9,
};
/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
struct v4l2_queryctrl {
__u32 id;
enum v4l2_ctrl_type type;
__u32 type; /* enum v4l2_ctrl_type */
__u8 name[32]; /* Whatever */
__s32 minimum; /* Note signedness */
__s32 maximum;
@@ -1170,9 +1300,12 @@ struct v4l2_queryctrl {
struct v4l2_querymenu {
__u32 id;
__u32 index;
__u8 name[32]; /* Whatever */
union {
__u8 name[32]; /* Whatever */
__s64 value;
};
__u32 reserved;
};
} __attribute__ ((packed));
/* Control flags */
#define V4L2_CTRL_FLAG_DISABLED 0x0001
@@ -1237,16 +1370,22 @@ enum v4l2_power_line_frequency {
#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30)
#define V4L2_CID_COLORFX (V4L2_CID_BASE+31)
enum v4l2_colorfx {
V4L2_COLORFX_NONE = 0,
V4L2_COLORFX_BW = 1,
V4L2_COLORFX_SEPIA = 2,
V4L2_COLORFX_NEGATIVE = 3,
V4L2_COLORFX_EMBOSS = 4,
V4L2_COLORFX_SKETCH = 5,
V4L2_COLORFX_SKY_BLUE = 6,
V4L2_COLORFX_GRASS_GREEN = 7,
V4L2_COLORFX_SKIN_WHITEN = 8,
V4L2_COLORFX_VIVID = 9,
V4L2_COLORFX_NONE = 0,
V4L2_COLORFX_BW = 1,
V4L2_COLORFX_SEPIA = 2,
V4L2_COLORFX_NEGATIVE = 3,
V4L2_COLORFX_EMBOSS = 4,
V4L2_COLORFX_SKETCH = 5,
V4L2_COLORFX_SKY_BLUE = 6,
V4L2_COLORFX_GRASS_GREEN = 7,
V4L2_COLORFX_SKIN_WHITEN = 8,
V4L2_COLORFX_VIVID = 9,
V4L2_COLORFX_AQUA = 10,
V4L2_COLORFX_ART_FREEZE = 11,
V4L2_COLORFX_SILHOUETTE = 12,
V4L2_COLORFX_SOLARIZATION = 13,
V4L2_COLORFX_ANTIQUE = 14,
V4L2_COLORFX_SET_CBCR = 15,
};
#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32)
#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33)
@@ -1263,9 +1402,10 @@ enum v4l2_colorfx {
#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40)
#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41)
#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42)
/* last CID + 1 */
#define V4L2_CID_LASTP1 (V4L2_CID_BASE+42)
#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43)
/* MPEG-class control IDs defined by V4L2 */
#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900)
@@ -1689,6 +1829,78 @@ enum v4l2_exposure_auto_type {
#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17)
#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18)
#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19)
#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20)
enum v4l2_auto_n_preset_white_balance {
V4L2_WHITE_BALANCE_MANUAL = 0,
V4L2_WHITE_BALANCE_AUTO = 1,
V4L2_WHITE_BALANCE_INCANDESCENT = 2,
V4L2_WHITE_BALANCE_FLUORESCENT = 3,
V4L2_WHITE_BALANCE_FLUORESCENT_H = 4,
V4L2_WHITE_BALANCE_HORIZON = 5,
V4L2_WHITE_BALANCE_DAYLIGHT = 6,
V4L2_WHITE_BALANCE_FLASH = 7,
V4L2_WHITE_BALANCE_CLOUDY = 8,
V4L2_WHITE_BALANCE_SHADE = 9,
};
#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE+21)
#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE+22)
#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE+23)
#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE+24)
enum v4l2_iso_sensitivity_auto_type {
V4L2_ISO_SENSITIVITY_MANUAL = 0,
V4L2_ISO_SENSITIVITY_AUTO = 1,
};
#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE+25)
enum v4l2_exposure_metering {
V4L2_EXPOSURE_METERING_AVERAGE = 0,
V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1,
V4L2_EXPOSURE_METERING_SPOT = 2,
};
#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE+26)
enum v4l2_scene_mode {
V4L2_SCENE_MODE_NONE = 0,
V4L2_SCENE_MODE_BACKLIGHT = 1,
V4L2_SCENE_MODE_BEACH_SNOW = 2,
V4L2_SCENE_MODE_CANDLE_LIGHT = 3,
V4L2_SCENE_MODE_DAWN_DUSK = 4,
V4L2_SCENE_MODE_FALL_COLORS = 5,
V4L2_SCENE_MODE_FIREWORKS = 6,
V4L2_SCENE_MODE_LANDSCAPE = 7,
V4L2_SCENE_MODE_NIGHT = 8,
V4L2_SCENE_MODE_PARTY_INDOOR = 9,
V4L2_SCENE_MODE_PORTRAIT = 10,
V4L2_SCENE_MODE_SPORTS = 11,
V4L2_SCENE_MODE_SUNSET = 12,
V4L2_SCENE_MODE_TEXT = 13,
};
#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE+27)
#define V4L2_LOCK_EXPOSURE (1 << 0)
#define V4L2_LOCK_WHITE_BALANCE (1 << 1)
#define V4L2_LOCK_FOCUS (1 << 2)
#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28)
#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29)
#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30)
#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0)
#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0)
#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1)
#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2)
#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE+31)
enum v4l2_auto_focus_range {
V4L2_AUTO_FOCUS_RANGE_AUTO = 0,
V4L2_AUTO_FOCUS_RANGE_NORMAL = 1,
V4L2_AUTO_FOCUS_RANGE_MACRO = 2,
V4L2_AUTO_FOCUS_RANGE_INFINITY = 3,
};
/* FM Modulator class control IDs */
#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900)
#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1)
@@ -1782,13 +1994,28 @@ enum v4l2_jpeg_chroma_subsampling {
#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17)
#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18)
/* Image source controls */
#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900)
#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1)
#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1)
#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2)
#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3)
/* Image processing controls */
#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900)
#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1)
#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1)
#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2)
/*
* T U N I N G
*/
struct v4l2_tuner {
__u32 index;
__u8 name[32];
enum v4l2_tuner_type type;
__u32 type; /* enum v4l2_tuner_type */
__u32 capability;
__u32 rangelow;
__u32 rangehigh;
@@ -1838,14 +2065,14 @@ struct v4l2_modulator {
struct v4l2_frequency {
__u32 tuner;
enum v4l2_tuner_type type;
__u32 type; /* enum v4l2_tuner_type */
__u32 frequency;
__u32 reserved[8];
};
struct v4l2_hw_freq_seek {
__u32 tuner;
enum v4l2_tuner_type type;
__u32 type; /* enum v4l2_tuner_type */
__u32 seek_upward;
__u32 wrap_around;
__u32 spacing;
@@ -2056,7 +2283,7 @@ struct v4l2_sliced_vbi_cap {
(equals frame lines 313-336 for 625 line video
standards, 263-286 for 525 line standards) */
__u16 service_lines[2][24];
enum v4l2_buf_type type;
__u32 type; /* enum v4l2_buf_type */
__u32 reserved[3]; /* must be 0 */
};
@@ -2137,8 +2364,8 @@ struct v4l2_plane_pix_format {
* @width: image width in pixels
* @height: image height in pixels
* @pixelformat: little endian four character code (fourcc)
* @field: field order (for interlaced video)
* @colorspace: supplemental to pixelformat
* @field: enum v4l2_field; field order (for interlaced video)
* @colorspace: enum v4l2_colorspace; supplemental to pixelformat
* @plane_fmt: per-plane information
* @num_planes: number of planes for this format
*/
@@ -2146,8 +2373,8 @@ struct v4l2_pix_format_mplane {
__u32 width;
__u32 height;
__u32 pixelformat;
enum v4l2_field field;
enum v4l2_colorspace colorspace;
__u32 field;
__u32 colorspace;
struct v4l2_plane_pix_format plane_fmt[VIDEO_MAX_PLANES];
__u8 num_planes;
@@ -2156,7 +2383,7 @@ struct v4l2_pix_format_mplane {
/**
* struct v4l2_format - stream data format
* @type: type of the data stream
* @type: enum v4l2_buf_type; type of the data stream
* @pix: definition of an image format
* @pix_mp: definition of a multiplanar image format
* @win: definition of an overlaid image
@@ -2165,7 +2392,7 @@ struct v4l2_pix_format_mplane {
* @raw_data: placeholder for future extensions and custom formats
*/
struct v4l2_format {
enum v4l2_buf_type type;
__u32 type;
union {
struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */
struct v4l2_pix_format_mplane pix_mp; /* V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE */
@@ -2179,7 +2406,7 @@ struct v4l2_format {
/* Stream type-dependent parameters
*/
struct v4l2_streamparm {
enum v4l2_buf_type type;
__u32 type; /* enum v4l2_buf_type */
union {
struct v4l2_captureparm capture;
struct v4l2_outputparm output;
@@ -2292,14 +2519,14 @@ struct v4l2_dbg_chip_ident {
* @index: on return, index of the first created buffer
* @count: entry: number of requested buffers,
* return: number of created buffers
* @memory: buffer memory type
* @memory: enum v4l2_memory; buffer memory type
* @format: frame format, for which buffers are requested
* @reserved: future extensions
*/
struct v4l2_create_buffers {
__u32 index;
__u32 count;
enum v4l2_memory memory;
__u32 memory;
struct v4l2_format format;
__u32 reserved[8];
};
@@ -2356,8 +2583,8 @@ struct v4l2_create_buffers {
#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format)
#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio)
#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout)
#define VIDIOC_G_PRIORITY _IOR('V', 67, enum v4l2_priority)
#define VIDIOC_S_PRIORITY _IOW('V', 68, enum v4l2_priority)
#define VIDIOC_G_PRIORITY _IOR('V', 67, __u32) /* enum v4l2_priority */
#define VIDIOC_S_PRIORITY _IOW('V', 68, __u32) /* enum v4l2_priority */
#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap)
#define VIDIOC_LOG_STATUS _IO('V', 70)
#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls)
@@ -2384,6 +2611,9 @@ struct v4l2_create_buffers {
#endif
#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek)
/* These four DV Preset ioctls are deprecated in favor of the DV Timings
ioctls. */
#define VIDIOC_ENUM_DV_PRESETS _IOWR('V', 83, struct v4l2_dv_enum_preset)
#define VIDIOC_S_DV_PRESET _IOWR('V', 84, struct v4l2_dv_preset)
#define VIDIOC_G_DV_PRESET _IOWR('V', 85, struct v4l2_dv_preset)
@@ -2408,6 +2638,12 @@ struct v4l2_create_buffers {
#define VIDIOC_DECODER_CMD _IOWR('V', 96, struct v4l2_decoder_cmd)
#define VIDIOC_TRY_DECODER_CMD _IOWR('V', 97, struct v4l2_decoder_cmd)
/* Experimental, these three ioctls may change over the next couple of kernel
versions. */
#define VIDIOC_ENUM_DV_TIMINGS _IOWR('V', 96, struct v4l2_enum_dv_timings)
#define VIDIOC_QUERY_DV_TIMINGS _IOR('V', 97, struct v4l2_dv_timings)
#define VIDIOC_DV_TIMINGS_CAP _IOWR('V', 98, struct v4l2_dv_timings_cap)
/* Reminder: when adding new ioctls please add support for them to
drivers/media/video/v4l2-compat-ioctl32.c as well! */

5
include/media/media-entity.h
View File

@@ -46,6 +46,7 @@ struct media_entity_operations {
int (*link_setup)(struct media_entity *entity,
const struct media_pad *local,
const struct media_pad *remote, u32 flags);
int (*link_validate)(struct media_link *link);
};
struct media_entity {
@@ -140,8 +141,8 @@ void media_entity_graph_walk_start(struct media_entity_graph *graph,
struct media_entity *entity);
struct media_entity *
media_entity_graph_walk_next(struct media_entity_graph *graph);
void media_entity_pipeline_start(struct media_entity *entity,
struct media_pipeline *pipe);
__must_check int media_entity_pipeline_start(struct media_entity *entity,
struct media_pipeline *pipe);
void media_entity_pipeline_stop(struct media_entity *entity);
#define media_entity_call(entity, operation, args...) \

19
include/media/mt9p031.h
View File

@@ -3,17 +3,18 @@
struct v4l2_subdev;
enum {
MT9P031_COLOR_VERSION,
MT9P031_MONOCHROME_VERSION,
};
/*
* struct mt9p031_platform_data - MT9P031 platform data
* @set_xclk: Clock frequency set callback
* @reset: Chip reset GPIO (set to -1 if not used)
* @ext_freq: Input clock frequency
* @target_freq: Pixel clock frequency
*/
struct mt9p031_platform_data {
int (*set_xclk)(struct v4l2_subdev *subdev, int hz);
int (*reset)(struct v4l2_subdev *subdev, int active);
int ext_freq; /* input frequency to the mt9p031 for PLL dividers */
int target_freq; /* frequency target for the PLL */
int version; /* MT9P031_COLOR_VERSION or MT9P031_MONOCHROME_VERSION */
int reset;
int ext_freq;
int target_freq;
};
#endif

29
include/media/omap3isp.h
View File

@@ -29,6 +29,10 @@
struct i2c_board_info;
struct isp_device;
#define ISP_XCLK_NONE 0
#define ISP_XCLK_A 1
#define ISP_XCLK_B 2
enum isp_interface_type {
ISP_INTERFACE_PARALLEL,
ISP_INTERFACE_CSI2A_PHY2,
@@ -86,6 +90,29 @@ enum {
ISP_CCP2_MODE_CCP2 = 1,
};
/**
* struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
* @pos: position of the lane
* @pol: polarity of the lane
*/
struct isp_csiphy_lane {
u8 pos;
u8 pol;
};
#define ISP_CSIPHY1_NUM_DATA_LANES 1
#define ISP_CSIPHY2_NUM_DATA_LANES 2
/**
* struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
* @data: Configuration of one or two data lanes
* @clk: Clock lane configuration
*/
struct isp_csiphy_lanes_cfg {
struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
struct isp_csiphy_lane clk;
};
/**
* struct isp_ccp2_platform_data - CCP2 interface platform data
* @strobe_clk_pol: Strobe/clock polarity
@@ -105,6 +132,7 @@ struct isp_ccp2_platform_data {
unsigned int ccp2_mode:1;
unsigned int phy_layer:1;
unsigned int vpclk_div:2;
struct isp_csiphy_lanes_cfg lanecfg;
};
/**
@@ -115,6 +143,7 @@ struct isp_ccp2_platform_data {
struct isp_csi2_platform_data {
unsigned crc:1;
unsigned vpclk_div:2;
struct isp_csiphy_lanes_cfg lanecfg;
};
struct isp_subdev_i2c_board_info {

3
include/media/rc-map.h
View File

@@ -62,6 +62,7 @@ void rc_map_init(void);
#define RC_MAP_ANYSEE "rc-anysee"
#define RC_MAP_APAC_VIEWCOMP "rc-apac-viewcomp"
#define RC_MAP_ASUS_PC39 "rc-asus-pc39"
#define RC_MAP_ASUS_PS3_100 "rc-asus-ps3-100"
#define RC_MAP_ATI_TV_WONDER_HD_600 "rc-ati-tv-wonder-hd-600"
#define RC_MAP_ATI_X10 "rc-ati-x10"
#define RC_MAP_AVERMEDIA_A16D "rc-avermedia-a16d"
@@ -113,6 +114,8 @@ void rc_map_init(void);
#define RC_MAP_LME2510 "rc-lme2510"
#define RC_MAP_MANLI "rc-manli"
#define RC_MAP_MEDION_X10 "rc-medion-x10"
#define RC_MAP_MEDION_X10_DIGITAINER "rc-medion-x10-digitainer"
#define RC_MAP_MEDION_X10_OR2X "rc-medion-x10-or2x"
#define RC_MAP_MSI_DIGIVOX_II "rc-msi-digivox-ii"
#define RC_MAP_MSI_DIGIVOX_III "rc-msi-digivox-iii"
#define RC_MAP_MSI_TVANYWHERE_PLUS "rc-msi-tvanywhere-plus"

16
include/media/s5p_fimc.h
View File

@@ -64,4 +64,20 @@ struct s5p_platform_fimc {
*/
#define S5P_FIMC_TX_END_NOTIFY _IO('e', 0)
enum fimc_subdev_index {
IDX_SENSOR,
IDX_CSIS,
IDX_FLITE,
IDX_FIMC,
IDX_MAX,
};
struct media_pipeline;
struct v4l2_subdev;
struct fimc_pipeline {
struct v4l2_subdev *subdevs[IDX_MAX];
struct media_pipeline *m_pipeline;
};
#endif /* S5P_FIMC_H_ */

4
include/media/saa7146.h
View File

@@ -13,12 +13,11 @@
#include <linux/mutex.h>
#include <linux/scatterlist.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <linux/vmalloc.h> /* for vmalloc() */
#include <linux/mm.h> /* for vmalloc_to_page() */
#define SAA7146_VERSION_CODE 0x000600 /* 0.6.0 */
#define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
#define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
@@ -121,6 +120,7 @@ struct saa7146_dev
struct list_head item;
struct v4l2_device v4l2_dev;
struct v4l2_ctrl_handler ctrl_handler;
/* different device locks */
spinlock_t slock;

25
include/media/saa7146_vv.h
View File

@@ -3,6 +3,7 @@
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-fh.h>
#include <media/saa7146.h>
#include <media/videobuf-dma-sg.h>
@@ -84,21 +85,15 @@ struct saa7146_overlay {
/* per open data */
struct saa7146_fh {
/* Must be the first field! */
struct v4l2_fh fh;
struct saa7146_dev *dev;
/* if this is a vbi or capture open */
enum v4l2_buf_type type;
/* video overlay */
struct saa7146_overlay ov;
/* video capture */
struct videobuf_queue video_q;
struct v4l2_pix_format video_fmt;
/* vbi capture */
struct videobuf_queue vbi_q;
struct v4l2_vbi_format vbi_fmt;
struct timer_list vbi_read_timeout;
unsigned int resources; /* resource management for device open */
};
@@ -109,7 +104,9 @@ struct saa7146_fh {
struct saa7146_vv
{
/* vbi capture */
struct saa7146_dmaqueue vbi_q;
struct saa7146_dmaqueue vbi_dmaq;
struct v4l2_vbi_format vbi_fmt;
struct timer_list vbi_read_timeout;
/* vbi workaround interrupt queue */
wait_queue_head_t vbi_wq;
int vbi_fieldcount;
@@ -119,13 +116,14 @@ struct saa7146_vv
struct saa7146_fh *video_fh;
/* video overlay */
struct saa7146_overlay ov;
struct v4l2_framebuffer ov_fb;
struct saa7146_format *ov_fmt;
struct saa7146_overlay *ov_data;
struct saa7146_fh *ov_suspend;
/* video capture */
struct saa7146_dmaqueue video_q;
struct saa7146_dmaqueue video_dmaq;
struct v4l2_pix_format video_fmt;
enum v4l2_field last_field;
/* common: fixme? shouldn't this be in saa7146_fh?
@@ -163,7 +161,8 @@ struct saa7146_ext_vv
int (*std_callback)(struct saa7146_dev*, struct saa7146_standard *);
/* the extension can override this */
struct v4l2_ioctl_ops ops;
struct v4l2_ioctl_ops vid_ops;
struct v4l2_ioctl_ops vbi_ops;
/* pointer to the saa7146 core ops */
const struct v4l2_ioctl_ops *core_ops;
@@ -202,10 +201,12 @@ void saa7146_set_gpio(struct saa7146_dev *saa, u8 pin, u8 data);
/* from saa7146_video.c */
extern const struct v4l2_ioctl_ops saa7146_video_ioctl_ops;
extern const struct v4l2_ioctl_ops saa7146_vbi_ioctl_ops;
extern struct saa7146_use_ops saa7146_video_uops;
int saa7146_start_preview(struct saa7146_fh *fh);
int saa7146_stop_preview(struct saa7146_fh *fh);
long saa7146_video_do_ioctl(struct file *file, unsigned int cmd, void *arg);
int saa7146_s_ctrl(struct v4l2_ctrl *ctrl);
/* from saa7146_vbi.c */
extern struct saa7146_use_ops saa7146_vbi_uops;

1
include/media/sh_mobile_ceu.h
View File

@@ -5,6 +5,7 @@
#define SH_CEU_FLAG_USE_16BIT_BUS (1 << 1) /* use 16bit bus width */
#define SH_CEU_FLAG_HSYNC_LOW (1 << 2) /* default High if possible */
#define SH_CEU_FLAG_VSYNC_LOW (1 << 3) /* default High if possible */
#define SH_CEU_FLAG_LOWER_8BIT (1 << 4) /* default upper 8bit */
struct device;
struct resource;

84
include/media/smiapp.h Normal file
View File

@@ -0,0 +1,84 @@
/*
* include/media/smiapp.h
*
* Generic driver for SMIA/SMIA++ compliant camera modules
*
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __SMIAPP_H_
#define __SMIAPP_H_
#include <media/v4l2-subdev.h>
#define SMIAPP_NAME "smiapp"
#define SMIAPP_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
#define SMIAPP_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0
#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1
#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2
#define SMIAPP_NO_XSHUTDOWN -1
/*
* Sometimes due to board layout considerations the camera module can be
* mounted rotated. The typical rotation used is 180 degrees which can be
* corrected by giving a default H-FLIP and V-FLIP in the sensor readout.
* FIXME: rotation also changes the bayer pattern.
*/
enum smiapp_module_board_orient {
SMIAPP_MODULE_BOARD_ORIENT_0 = 0,
SMIAPP_MODULE_BOARD_ORIENT_180,
};
struct smiapp_flash_strobe_parms {
u8 mode;
u32 strobe_width_high_us;
u16 strobe_delay;
u16 stobe_start_point;
u8 trigger;
};
struct smiapp_platform_data {
/*
* Change the cci address if i2c_addr_alt is set.
* Both default and alternate cci addr need to be present
*/
unsigned short i2c_addr_dfl; /* Default i2c addr */
unsigned short i2c_addr_alt; /* Alternate i2c addr */
unsigned int nvm_size; /* bytes */
unsigned int ext_clk; /* sensor external clk */
unsigned int lanes; /* Number of CSI-2 lanes */
u8 csi_signalling_mode; /* SMIAPP_CSI_SIGNALLING_MODE_* */
const s64 *op_sys_clock;
enum smiapp_module_board_orient module_board_orient;
struct smiapp_flash_strobe_parms *strobe_setup;
int (*set_xclk)(struct v4l2_subdev *sd, int hz);
char *ext_clk_name;
int xshutdown; /* gpio or SMIAPP_NO_XSHUTDOWN */
};
#endif /* __SMIAPP_H_ */

6
include/media/soc_camera.h
View File

@@ -56,11 +56,15 @@ struct soc_camera_device {
};
};
/* Host supports programmable stride */
#define SOCAM_HOST_CAP_STRIDE (1 << 0)
struct soc_camera_host {
struct v4l2_device v4l2_dev;
struct list_head list;
struct mutex host_lock; /* Protect during probing */
unsigned char nr; /* Host number */
u32 capabilities;
void *priv;
const char *drv_name;
struct soc_camera_host_ops *ops;
@@ -98,7 +102,7 @@ struct soc_camera_host_ops {
int (*set_bus_param)(struct soc_camera_device *);
int (*get_parm)(struct soc_camera_device *, struct v4l2_streamparm *);
int (*set_parm)(struct soc_camera_device *, struct v4l2_streamparm *);
int (*enum_fsizes)(struct soc_camera_device *, struct v4l2_frmsizeenum *);
int (*enum_framesizes)(struct soc_camera_device *, struct v4l2_frmsizeenum *);
unsigned int (*poll)(struct file *, poll_table *);
};

21
include/media/soc_mediabus.h
View File

@@ -46,6 +46,24 @@ enum soc_mbus_order {
SOC_MBUS_ORDER_BE,
};
/**
* enum soc_mbus_layout - planes layout in memory
* @SOC_MBUS_LAYOUT_PACKED: color components packed
* @SOC_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored in 3 planes (4:2:2)
* @SOC_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored in a luma and a
* chroma plane (C plane is half the size
* of Y plane)
* @SOC_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored in a luma and a
* chroma plane (C plane is the same size
* as Y plane)
*/
enum soc_mbus_layout {
SOC_MBUS_LAYOUT_PACKED = 0,
SOC_MBUS_LAYOUT_PLANAR_2Y_U_V,
SOC_MBUS_LAYOUT_PLANAR_2Y_C,
SOC_MBUS_LAYOUT_PLANAR_Y_C,
};
/**
* struct soc_mbus_pixelfmt - Data format on the media bus
* @name: Name of the format
@@ -60,6 +78,7 @@ struct soc_mbus_pixelfmt {
u32 fourcc;
enum soc_mbus_packing packing;
enum soc_mbus_order order;
enum soc_mbus_layout layout;
u8 bits_per_sample;
};
@@ -80,6 +99,8 @@ const struct soc_mbus_pixelfmt *soc_mbus_find_fmtdesc(
const struct soc_mbus_pixelfmt *soc_mbus_get_fmtdesc(
enum v4l2_mbus_pixelcode code);
s32 soc_mbus_bytes_per_line(u32 width, const struct soc_mbus_pixelfmt *mf);
s32 soc_mbus_image_size(const struct soc_mbus_pixelfmt *mf,
u32 bytes_per_line, u32 height);
int soc_mbus_samples_per_pixel(const struct soc_mbus_pixelfmt *mf,
unsigned int *numerator, unsigned int *denominator);
unsigned int soc_mbus_config_compatible(const struct v4l2_mbus_config *cfg,

40
include/media/v4l2-ctrls.h
View File

@@ -25,6 +25,7 @@
#include <linux/videodev2.h>
/* forward references */
struct file;
struct v4l2_ctrl_handler;
struct v4l2_ctrl_helper;
struct v4l2_ctrl;
@@ -129,7 +130,10 @@ struct v4l2_ctrl {
u32 step;
u32 menu_skip_mask;
};
const char * const *qmenu;
union {
const char * const *qmenu;
const s64 *qmenu_int;
};
unsigned long flags;
union {
s32 val;
@@ -164,7 +168,9 @@ struct v4l2_ctrl_ref {
/** struct v4l2_ctrl_handler - The control handler keeps track of all the
* controls: both the controls owned by the handler and those inherited
* from other handlers.
* @_lock: Default for "lock".
* @lock: Lock to control access to this handler and its controls.
* May be replaced by the user right after init.
* @ctrls: The list of controls owned by this handler.
* @ctrl_refs: The list of control references.
* @cached: The last found control reference. It is common that the same
@@ -175,7 +181,8 @@ struct v4l2_ctrl_ref {
* @error: The error code of the first failed control addition.
*/
struct v4l2_ctrl_handler {
struct mutex lock;
struct mutex _lock;
struct mutex *lock;
struct list_head ctrls;
struct list_head ctrl_refs;
struct v4l2_ctrl_ref *cached;
@@ -219,6 +226,7 @@ struct v4l2_ctrl_config {
u32 flags;
u32 menu_skip_mask;
const char * const *qmenu;
const s64 *qmenu_int;
unsigned int is_private:1;
};
@@ -343,6 +351,23 @@ struct v4l2_ctrl *v4l2_ctrl_new_std_menu(struct v4l2_ctrl_handler *hdl,
const struct v4l2_ctrl_ops *ops,
u32 id, s32 max, s32 mask, s32 def);
/** v4l2_ctrl_new_int_menu() - Create a new standard V4L2 integer menu control.
* @hdl: The control handler.
* @ops: The control ops.
* @id: The control ID.
* @max: The control's maximum value.
* @def: The control's default value.
* @qmenu_int: The control's menu entries.
*
* Same as v4l2_ctrl_new_std_menu(), but @mask is set to 0 and it additionaly
* takes as an argument an array of integers determining the menu items.
*
* If @id refers to a non-integer-menu control, then this function will return NULL.
*/
struct v4l2_ctrl *v4l2_ctrl_new_int_menu(struct v4l2_ctrl_handler *hdl,
const struct v4l2_ctrl_ops *ops,
u32 id, s32 max, s32 def, const s64 *qmenu_int);
/** v4l2_ctrl_add_ctrl() - Add a control from another handler to this handler.
* @hdl: The control handler.
* @ctrl: The control to add.
@@ -451,7 +476,7 @@ void v4l2_ctrl_grab(struct v4l2_ctrl *ctrl, bool grabbed);
*/
static inline void v4l2_ctrl_lock(struct v4l2_ctrl *ctrl)
{
mutex_lock(&ctrl->handler->lock);
mutex_lock(ctrl->handler->lock);
}
/** v4l2_ctrl_lock() - Helper function to unlock the handler
@@ -460,7 +485,7 @@ static inline void v4l2_ctrl_lock(struct v4l2_ctrl *ctrl)
*/
static inline void v4l2_ctrl_unlock(struct v4l2_ctrl *ctrl)
{
mutex_unlock(&ctrl->handler->lock);
mutex_unlock(ctrl->handler->lock);
}
/** v4l2_ctrl_g_ctrl() - Helper function to get the control's value from within a driver.
@@ -487,10 +512,9 @@ s32 v4l2_ctrl_g_ctrl(struct v4l2_ctrl *ctrl);
int v4l2_ctrl_s_ctrl(struct v4l2_ctrl *ctrl, s32 val);
/* Internal helper functions that deal with control events. */
void v4l2_ctrl_add_event(struct v4l2_ctrl *ctrl,
struct v4l2_subscribed_event *sev);
void v4l2_ctrl_del_event(struct v4l2_ctrl *ctrl,
struct v4l2_subscribed_event *sev);
extern const struct v4l2_subscribed_event_ops v4l2_ctrl_sub_ev_ops;
void v4l2_ctrl_replace(struct v4l2_event *old, const struct v4l2_event *new);
void v4l2_ctrl_merge(const struct v4l2_event *old, struct v4l2_event *new);
/* Can be used as a vidioc_log_status function that just dumps all controls
associated with the filehandle. */

25
include/media/v4l2-dev.h
View File

@@ -39,6 +39,9 @@ struct v4l2_ctrl_handler;
#define V4L2_FL_USES_V4L2_FH (1)
/* Use the prio field of v4l2_fh for core priority checking */
#define V4L2_FL_USE_FH_PRIO (2)
/* If ioctl core locking is in use, then apply that also to all
file operations. Don't use this flag in new drivers! */
#define V4L2_FL_LOCK_ALL_FOPS (3)
/* Priority helper functions */
@@ -126,8 +129,10 @@ struct video_device
/* ioctl callbacks */
const struct v4l2_ioctl_ops *ioctl_ops;
DECLARE_BITMAP(valid_ioctls, BASE_VIDIOC_PRIVATE);
/* serialization lock */
DECLARE_BITMAP(disable_locking, BASE_VIDIOC_PRIVATE);
struct mutex *lock;
};
@@ -173,6 +178,26 @@ void video_device_release(struct video_device *vdev);
a dubious construction at best. */
void video_device_release_empty(struct video_device *vdev);
/* returns true if cmd is a known V4L2 ioctl */
bool v4l2_is_known_ioctl(unsigned int cmd);
/* mark that this command shouldn't use core locking */
static inline void v4l2_disable_ioctl_locking(struct video_device *vdev, unsigned int cmd)
{
if (_IOC_NR(cmd) < BASE_VIDIOC_PRIVATE)
set_bit(_IOC_NR(cmd), vdev->disable_locking);
}
/* Mark that this command isn't implemented. This must be called before
video_device_register. See also the comments in determine_valid_ioctls().
This function allows drivers to provide just one v4l2_ioctl_ops struct, but
disable ioctls based on the specific card that is actually found. */
static inline void v4l2_disable_ioctl(struct video_device *vdev, unsigned int cmd)
{
if (_IOC_NR(cmd) < BASE_VIDIOC_PRIVATE)
set_bit(_IOC_NR(cmd), vdev->valid_ioctls);
}
/* helper functions to access driver private data. */
static inline void *video_get_drvdata(struct video_device *vdev)
{

24
include/media/v4l2-event.h
View File

@@ -78,6 +78,19 @@ struct v4l2_kevent {
struct v4l2_event event;
};
/** struct v4l2_subscribed_event_ops - Subscribed event operations.
* @add: Optional callback, called when a new listener is added
* @del: Optional callback, called when a listener stops listening
* @replace: Optional callback that can replace event 'old' with event 'new'.
* @merge: Optional callback that can merge event 'old' into event 'new'.
*/
struct v4l2_subscribed_event_ops {
int (*add)(struct v4l2_subscribed_event *sev, unsigned elems);
void (*del)(struct v4l2_subscribed_event *sev);
void (*replace)(struct v4l2_event *old, const struct v4l2_event *new);
void (*merge)(const struct v4l2_event *old, struct v4l2_event *new);
};
/** struct v4l2_subscribed_event - Internal struct representing a subscribed event.
* @list: List node for the v4l2_fh->subscribed list.
* @type: Event type.
@@ -85,8 +98,7 @@ struct v4l2_kevent {
* @flags: Copy of v4l2_event_subscription->flags.
* @fh: Filehandle that subscribed to this event.
* @node: List node that hooks into the object's event list (if there is one).
* @replace: Optional callback that can replace event 'old' with event 'new'.
* @merge: Optional callback that can merge event 'old' into event 'new'.
* @ops: v4l2_subscribed_event_ops
* @elems: The number of elements in the events array.
* @first: The index of the events containing the oldest available event.
* @in_use: The number of queued events.
@@ -99,10 +111,7 @@ struct v4l2_subscribed_event {
u32 flags;
struct v4l2_fh *fh;
struct list_head node;
void (*replace)(struct v4l2_event *old,
const struct v4l2_event *new);
void (*merge)(const struct v4l2_event *old,
struct v4l2_event *new);
const struct v4l2_subscribed_event_ops *ops;
unsigned elems;
unsigned first;
unsigned in_use;
@@ -115,7 +124,8 @@ void v4l2_event_queue(struct video_device *vdev, const struct v4l2_event *ev);
void v4l2_event_queue_fh(struct v4l2_fh *fh, const struct v4l2_event *ev);
int v4l2_event_pending(struct v4l2_fh *fh);
int v4l2_event_subscribe(struct v4l2_fh *fh,
struct v4l2_event_subscription *sub, unsigned elems);
struct v4l2_event_subscription *sub, unsigned elems,
const struct v4l2_subscribed_event_ops *ops);
int v4l2_event_unsubscribe(struct v4l2_fh *fh,
struct v4l2_event_subscription *sub);
void v4l2_event_unsubscribe_all(struct v4l2_fh *fh);

6
include/media/v4l2-ioctl.h
View File

@@ -271,6 +271,12 @@ struct v4l2_ioctl_ops {
struct v4l2_dv_timings *timings);
int (*vidioc_g_dv_timings) (struct file *file, void *fh,
struct v4l2_dv_timings *timings);
int (*vidioc_query_dv_timings) (struct file *file, void *fh,
struct v4l2_dv_timings *timings);
int (*vidioc_enum_dv_timings) (struct file *file, void *fh,
struct v4l2_enum_dv_timings *timings);
int (*vidioc_dv_timings_cap) (struct file *file, void *fh,
struct v4l2_dv_timings_cap *cap);
int (*vidioc_subscribe_event) (struct v4l2_fh *fh,
struct v4l2_event_subscription *sub);

53
include/media/v4l2-subdev.h
View File

@@ -307,6 +307,12 @@ struct v4l2_subdev_video_ops {
struct v4l2_dv_timings *timings);
int (*g_dv_timings)(struct v4l2_subdev *sd,
struct v4l2_dv_timings *timings);
int (*enum_dv_timings)(struct v4l2_subdev *sd,
struct v4l2_enum_dv_timings *timings);
int (*query_dv_timings)(struct v4l2_subdev *sd,
struct v4l2_dv_timings *timings);
int (*dv_timings_cap)(struct v4l2_subdev *sd,
struct v4l2_dv_timings_cap *cap);
int (*enum_mbus_fmt)(struct v4l2_subdev *sd, unsigned int index,
enum v4l2_mbus_pixelcode *code);
int (*enum_mbus_fsizes)(struct v4l2_subdev *sd,
@@ -466,6 +472,15 @@ struct v4l2_subdev_pad_ops {
struct v4l2_subdev_crop *crop);
int (*get_crop)(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
struct v4l2_subdev_crop *crop);
int (*get_selection)(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
struct v4l2_subdev_selection *sel);
int (*set_selection)(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
struct v4l2_subdev_selection *sel);
#ifdef CONFIG_MEDIA_CONTROLLER
int (*link_validate)(struct v4l2_subdev *sd, struct media_link *link,
struct v4l2_subdev_format *source_fmt,
struct v4l2_subdev_format *sink_fmt);
#endif /* CONFIG_MEDIA_CONTROLLER */
};
struct v4l2_subdev_ops {
@@ -541,7 +556,7 @@ struct v4l2_subdev {
#define media_entity_to_v4l2_subdev(ent) \
container_of(ent, struct v4l2_subdev, entity)
#define vdev_to_v4l2_subdev(vdev) \
video_get_drvdata(vdev)
((struct v4l2_subdev *)video_get_drvdata(vdev))
/*
* Used for storing subdev information per file handle
@@ -549,8 +564,11 @@ struct v4l2_subdev {
struct v4l2_subdev_fh {
struct v4l2_fh vfh;
#if defined(CONFIG_VIDEO_V4L2_SUBDEV_API)
struct v4l2_mbus_framefmt *try_fmt;
struct v4l2_rect *try_crop;
struct {
struct v4l2_mbus_framefmt try_fmt;
struct v4l2_rect try_crop;
struct v4l2_rect try_compose;
} *pad;
#endif
};
@@ -558,17 +576,19 @@ struct v4l2_subdev_fh {
container_of(fh, struct v4l2_subdev_fh, vfh)
#if defined(CONFIG_VIDEO_V4L2_SUBDEV_API)
static inline struct v4l2_mbus_framefmt *
v4l2_subdev_get_try_format(struct v4l2_subdev_fh *fh, unsigned int pad)
{
return &fh->try_fmt[pad];
}
#define __V4L2_SUBDEV_MK_GET_TRY(rtype, fun_name, field_name) \
static inline struct rtype * \
v4l2_subdev_get_try_##fun_name(struct v4l2_subdev_fh *fh, \
unsigned int pad) \
{ \
BUG_ON(unlikely(pad >= vdev_to_v4l2_subdev( \
fh->vfh.vdev)->entity.num_pads)); \
return &fh->pad[pad].field_name; \
}
static inline struct v4l2_rect *
v4l2_subdev_get_try_crop(struct v4l2_subdev_fh *fh, unsigned int pad)
{
return &fh->try_crop[pad];
}
__V4L2_SUBDEV_MK_GET_TRY(v4l2_mbus_framefmt, format, try_fmt)
__V4L2_SUBDEV_MK_GET_TRY(v4l2_rect, crop, try_compose)
__V4L2_SUBDEV_MK_GET_TRY(v4l2_rect, compose, try_compose)
#endif
extern const struct v4l2_file_operations v4l2_subdev_fops;
@@ -593,6 +613,13 @@ static inline void *v4l2_get_subdev_hostdata(const struct v4l2_subdev *sd)
return sd->host_priv;
}
#ifdef CONFIG_MEDIA_CONTROLLER
int v4l2_subdev_link_validate_default(struct v4l2_subdev *sd,
struct media_link *link,
struct v4l2_subdev_format *source_fmt,
struct v4l2_subdev_format *sink_fmt);
int v4l2_subdev_link_validate(struct media_link *link);
#endif /* CONFIG_MEDIA_CONTROLLER */
void v4l2_subdev_init(struct v4l2_subdev *sd,
const struct v4l2_subdev_ops *ops);

10
include/media/videobuf-dma-contig.h
View File

@@ -26,6 +26,16 @@ void videobuf_queue_dma_contig_init(struct videobuf_queue *q,
void *priv,
struct mutex *ext_lock);
void videobuf_queue_dma_contig_init_cached(struct videobuf_queue *q,
const struct videobuf_queue_ops *ops,
struct device *dev,
spinlock_t *irqlock,
enum v4l2_buf_type type,
enum v4l2_field field,
unsigned int msize,
void *priv,
struct mutex *ext_lock);
dma_addr_t videobuf_to_dma_contig(struct videobuf_buffer *buf);
void videobuf_dma_contig_free(struct videobuf_queue *q,
struct videobuf_buffer *buf);