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x86/apic: Support 15 bits of APIC ID in MSI where available

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Some hypervisors can allow the guest to use the Extended Destination ID
field in the MSI address to address up to 32768 CPUs.

This applies to all downstream devices which generate MSI cycles,
including HPET, I/O-APIC and PCI MSI.

HPET and PCI MSI use the same __irq_msi_compose_msg() function, while
I/O-APIC generates its own and had support for the extended bits added in
a previous commit.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20201024213535.443185-33-dwmw2@infradead.org
This commit is contained in:
David Woodhouse
2020-10-24 22:35:32 +01:00
committed by Thomas Gleixner
parent 51130d2188
commit ab0f59c6f1
4 changed files with 29 additions and 3 deletions
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3
arch/x86/include/asm/msi.h
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@@ -29,7 +29,8 @@ typedef struct x86_msi_addr_lo {
u32 reserved_0 : 2,
dest_mode_logical : 1,
redirect_hint : 1,
reserved_1 : 8,
reserved_1 : 1,
virt_destid_8_14 : 7,
destid_0_7 : 8,
base_address : 12;
};