forked from Minki/linux
staging: sb105x: delete the driver
It's been marked BROKEN for over a year, and no one has stepped up to do anything with the code, and no one has complained. So just delete it. If someone wants to fix it up and merge it "properly", they can revert this commit. Cc: Jiri Slaby <jslaby@suse.cz> Cc: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
parent
aee0bda81b
commit
aa98b772b7
@ -124,8 +124,6 @@ source "drivers/staging/imx-drm/Kconfig"
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source "drivers/staging/dgrp/Kconfig"
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source "drivers/staging/sb105x/Kconfig"
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source "drivers/staging/fwserial/Kconfig"
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source "drivers/staging/goldfish/Kconfig"
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@ -55,7 +55,6 @@ obj-$(CONFIG_NET_VENDOR_SILICOM) += silicom/
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obj-$(CONFIG_CED1401) += ced1401/
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obj-$(CONFIG_DRM_IMX) += imx-drm/
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obj-$(CONFIG_DGRP) += dgrp/
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obj-$(CONFIG_SB105X) += sb105x/
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obj-$(CONFIG_FIREWIRE_SERIAL) += fwserial/
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obj-$(CONFIG_GOLDFISH) += goldfish/
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obj-$(CONFIG_LUSTRE_FS) += lustre/
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@ -1,9 +0,0 @@
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config SB105X
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tristate "SystemBase PCI Multiport UART"
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select SERIAL_CORE
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depends on PCI && X86 && TTY && BROKEN
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help
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A driver for the SystemBase Multi-2/PCI serial card
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To compile this driver a module, choose M here: the module
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will be called "sb105x".
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@ -1,3 +0,0 @@
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obj-$(CONFIG_SB105X) += sb105x.o
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sb105x-y := sb_pci_mp.o
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@ -1,295 +0,0 @@
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/*
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* SB105X_UART.h
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*
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* Copyright (C) 2008 systembase
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*
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* UART registers.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef UART_SB105X_H
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#define UART_SB105X_H
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/*
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* option register
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*/
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/* Device Information Register */
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#define MP_OPTR_DIR0 0x04 /* port0 ~ port8 */
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#define MP_OPTR_DIR1 0x05 /* port8 ~ port15 */
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#define MP_OPTR_DIR2 0x06 /* port16 ~ port23 */
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#define MP_OPTR_DIR3 0x07 /* port24 ~ port31 */
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#define DIR_UART_16C550 0
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#define DIR_UART_16C1050 1
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#define DIR_UART_16C1050A 2
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#define DIR_CLK_1843200 0x0 /* input clock 1843200 Hz */
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#define DIR_CLK_3686400 0x1 /* input clock 3686400 Hz */
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#define DIR_CLK_7372800 0x2 /* input clock 7372800 Hz */
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#define DIR_CLK_14745600 0x3 /* input clock 14745600 Hz */
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#define DIR_CLK_29491200 0x4 /* input clock 29491200 Hz */
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#define DIR_CLK_58985400 0x5 /* input clock 58985400 Hz */
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/* Interface Information Register */
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#define MP_OPTR_IIR0 0x08 /* port0 ~ port8 */
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#define MP_OPTR_IIR1 0x09 /* port8 ~ port15 */
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#define MP_OPTR_IIR2 0x0A /* port16 ~ port23 */
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#define MP_OPTR_IIR3 0x0B /* port24 ~ port31 */
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#define IIR_RS232 0x00 /* RS232 type */
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#define IIR_RS422 0x10 /* RS422 type */
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#define IIR_RS485 0x20 /* RS485 type */
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#define IIR_TYPE_MASK 0x30
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/* Interrupt Mask Register */
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#define MP_OPTR_IMR0 0x0C /* port0 ~ port8 */
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#define MP_OPTR_IMR1 0x0D /* port8 ~ port15 */
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#define MP_OPTR_IMR2 0x0E /* port16 ~ port23 */
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#define MP_OPTR_IMR3 0x0F /* port24 ~ port31 */
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/* Interrupt Poll Register */
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#define MP_OPTR_IPR0 0x10 /* port0 ~ port8 */
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#define MP_OPTR_IPR1 0x11 /* port8 ~ port15 */
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#define MP_OPTR_IPR2 0x12 /* port16 ~ port23 */
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#define MP_OPTR_IPR3 0x13 /* port24 ~ port31 */
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/* General Purpose Output Control Register */
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#define MP_OPTR_GPOCR 0x20
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/* General Purpose Output Data Register */
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#define MP_OPTR_GPODR 0x21
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/* Parallel Additional Function Register */
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#define MP_OPTR_PAFR 0x23
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/*
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* systembase 16c105x UART register
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*/
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#define PAGE_0 0
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#define PAGE_1 1
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#define PAGE_2 2
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#define PAGE_3 3
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#define PAGE_4 4
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/*
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* ******************************************************************
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* * DLAB=0 =============== Page 0 Registers *
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* ******************************************************************
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*/
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#define SB105X_RX 0 /* In: Receive buffer */
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#define SB105X_TX 0 /* Out: Transmit buffer */
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#define SB105X_IER 1 /* Out: Interrupt Enable Register */
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#define SB105X_IER_CTSI 0x80 /* CTS# Interrupt Enable (Requires EFR[4] = 1) */
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#define SB105X_IER_RTSI 0x40 /* RTS# Interrupt Enable (Requires EFR[4] = 1) */
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#define SB105X_IER_XOI 0x20 /* Xoff Interrupt Enable (Requires EFR[4] = 1) */
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#define SB105X_IER_SME 0x10 /* Sleep Mode Enable (Requires EFR[4] = 1) */
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#define SB105X_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define SB105X_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define SB105X_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define SB105X_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define SB105X_ISR 2 /* In: Interrupt ID Register */
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#define SB105X_ISR_NOINT 0x01 /* No interrupts pending */
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#define SB105X_ISR_RLSI 0x06 /* Receiver line status interrupt (Priority = 1)*/
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#define SB105X_ISR_RDAI 0x0c /* Receive Data Available interrupt */
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#define SB105X_ISR_CTII 0x04 /* Character Timeout Indication interrupt */
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#define SB105X_ISR_THRI 0x02 /* Transmitter holding register empty */
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#define SB105X_ISR_MSI 0x00 /* Modem status interrupt */
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#define SB105X_ISR_RXCI 0x10 /* Receive Xoff or Special Character interrupt */
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#define SB105X_ISR_RCSI 0x20 /* RTS#, CTS# status interrupt during Auto RTS/CTS flow control */
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#define SB105X_FCR 2 /* Out: FIFO Control Register */
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#define SB105X_FCR_FEN 0x01 /* FIFO Enable */
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#define SB105X_FCR_RXFR 0x02 /* RX FIFO Reset */
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#define SB105X_FCR_TXFR 0x04 /* TX FIFO Reset */
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#define SB105X_FCR_DMS 0x08 /* DMA Mode Select */
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#define SB105X_FCR_RTR08 0x00 /* Receive Trigger Level set at 8 */
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#define SB105X_FCR_RTR16 0x40 /* Receive Trigger Level set at 16 */
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#define SB105X_FCR_RTR56 0x80 /* Receive Trigger Level set at 56 */
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#define SB105X_FCR_RTR60 0xc0 /* Receive Trigger Level set at 60 */
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#define SB105X_FCR_TTR08 0x00 /* Transmit Trigger Level set at 8 */
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#define SB105X_FCR_TTR16 0x10 /* Transmit Trigger Level set at 16 */
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#define SB105X_FCR_TTR32 0x20 /* Transmit Trigger Level set at 32 */
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#define SB105X_FCR_TTR56 0x30 /* Transmit Trigger Level set at 56 */
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#define SB105X_LCR 3 /* Out: Line Control Register */
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/*
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* * Note: if the word length is 5 bits (SB105X_LCR_WLEN5), then setting
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* * SB105X_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
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*/
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#define SB105X_LCR_DLAB 0x80 /* Divisor Latch Enable */
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#define SB105X_LCR_SBC 0x40 /* Break Enable*/
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#define SB105X_LCR_SPAR 0x20 /* Set Stick parity */
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#define SB105X_LCR_EPAR 0x10 /* Even parity select */
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#define SB105X_LCR_PAREN 0x08 /* Parity Enable */
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#define SB105X_LCR_STOP 0x04 /* Stop bits: 0->1 bit, 1->2 bits, 1 and SB105X_LCR_WLEN5 -> 1.5 bit */
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#define SB105X_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define SB105X_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define SB105X_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define SB105X_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define SB105X_LCR_BF 0xBF
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#define SB105X_MCR 4 /* Out: Modem Control Register */
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#define SB105X_MCR_CPS 0x80 /* Clock Prescaler Select */
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#define SB105X_MCR_P2S 0x40 /* Page 2 Select /Xoff Re-Transmit Access Enable */
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#define SB105X_MCR_XOA 0x20 /* Xon Any Enable */
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#define SB105X_MCR_ILB 0x10 /* Internal Loopback Enable */
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#define SB105X_MCR_OUT2 0x08 /* Out2/Interrupt Output Enable*/
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#define SB105X_MCR_OUT1 0x04 /* Out1/Interrupt Output Enable */
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#define SB105X_MCR_RTS 0x02 /* RTS# Output */
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#define SB105X_MCR_DTR 0x01 /* DTR# Output */
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#define SB105X_LSR 5 /* In: Line Status Register */
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#define SB105X_LSR_RFEI 0x80 /* Receive FIFO data error Indicator */
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#define SB105X_LSR_TEMI 0x40 /* THR and TSR Empty Indicator */
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#define SB105X_LSR_THRE 0x20 /* THR Empty Indicator */
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#define SB105X_LSR_BII 0x10 /* Break interrupt indicator */
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#define SB105X_LSR_FEI 0x08 /* Frame error indicator */
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#define SB105X_LSR_PEI 0x04 /* Parity error indicator */
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#define SB105X_LSR_OEI 0x02 /* Overrun error indicator */
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#define SB105X_LSR_RDRI 0x01 /* Receive data ready Indicator*/
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#define SB105X_MSR 6 /* In: Modem Status Register */
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#define SB105X_MSR_DCD 0x80 /* Data Carrier Detect */
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#define SB105X_MSR_RI 0x40 /* Ring Indicator */
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#define SB105X_MSR_DSR 0x20 /* Data Set Ready */
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#define SB105X_MSR_CTS 0x10 /* Clear to Send */
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#define SB105X_MSR_DDCD 0x08 /* Delta DCD */
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#define SB105X_MSR_DRI 0x04 /* Delta ring indicator */
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#define SB105X_MSR_DDSR 0x02 /* Delta DSR */
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#define SB105X_MSR_DCTS 0x01 /* Delta CTS */
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#define SB105XA_MDR 6 /* Out: Multi Drop mode Register */
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#define SB105XA_MDR_NPS 0x08 /* 9th Bit Polarity Select */
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#define SB105XA_MDR_AME 0x02 /* Auto Multi-drop Enable */
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#define SB105XA_MDR_MDE 0x01 /* Multi Drop Enable */
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#define SB105X_SPR 7 /* I/O: Scratch Register */
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/*
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* DLAB=1
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*/
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#define SB105X_DLL 0 /* Out: Divisor Latch Low */
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#define SB105X_DLM 1 /* Out: Divisor Latch High */
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/*
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* ******************************************************************
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* * DLAB(LCR[7]) = 0 , MCR[6] = 1 ============= Page 2 Registers *
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* ******************************************************************
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*/
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#define SB105X_GICR 1 /* Global Interrupt Control Register */
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#define SB105X_GICR_GIM 0x01 /* Global Interrupt Mask */
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#define SB105X_GISR 2 /* Global Interrupt Status Register */
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#define SB105X_GISR_MGICR0 0x80 /* Mirror the content of GICR[0] */
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#define SB105X_GISR_CS3IS 0x08 /* SB105X of CS3# Interrupt Status */
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#define SB105X_GISR_CS2IS 0x04 /* SB105X of CS2# Interrupt Status */
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#define SB105X_GISR_CS1IS 0x02 /* SB105X of CS1# Interrupt Status */
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#define SB105X_GISR_CS0IS 0x01 /* SB105X of CS0# Interrupt Status */
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#define SB105X_TFCR 5 /* Transmit FIFO Count Register */
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#define SB105X_RFCR 6 /* Receive FIFO Count Register */
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#define SB105X_FSR 7 /* Flow Control Status Register */
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#define SB105X_FSR_THFS 0x20 /* Transmit Hardware Flow Control Status */
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#define SB105X_FSR_TSFS 0x10 /* Transmit Software Flow Control Status */
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#define SB105X_FSR_RHFS 0x02 /* Receive Hardware Flow Control Status */
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#define SB105X_FSR_RSFS 0x01 /* Receive Software Flow Control Status */
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/*
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* ******************************************************************
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* * LCR = 0xBF, PSR[0] = 0 ============= Page 3 Registers *
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* ******************************************************************
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*/
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#define SB105X_PSR 0 /* Page Select Register */
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#define SB105X_PSR_P3KEY 0xA4 /* Page 3 Select Key */
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#define SB105X_PSR_P4KEY 0xA5 /* Page 5 Select Key */
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#define SB105X_ATR 1 /* Auto Toggle Control Register */
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#define SB105X_ATR_RPS 0x80 /* RXEN Polarity Select */
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#define SB105X_ATR_RCMS 0x40 /* RXEN Control Mode Select */
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#define SB105X_ATR_TPS 0x20 /* TXEN Polarity Select */
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#define SB105X_ATR_TCMS 0x10 /* TXEN Control Mode Select */
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#define SB105X_ATR_ATDIS 0x00 /* Auto Toggle is disabled */
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#define SB105X_ATR_ART 0x01 /* RTS#/TXEN pin operates as TXEN */
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#define SB105X_ATR_ADT 0x02 /* DTR#/TXEN pin operates as TXEN */
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#define SB105X_ATR_A80 0x03 /* only in 80 pin use */
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#define SB105X_EFR 2 /* (Auto) Enhanced Feature Register */
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#define SB105X_EFR_ACTS 0x80 /* Auto-CTS Flow Control Enable */
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#define SB105X_EFR_ARTS 0x40 /* Auto-RTS Flow Control Enable */
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#define SB105X_EFR_SCD 0x20 /* Special Character Detect */
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#define SB105X_EFR_EFBEN 0x10 /* Enhanced Function Bits Enable */
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#define SB105X_XON1 4 /* Xon1 Character Register */
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#define SB105X_XON2 5 /* Xon2 Character Register */
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#define SB105X_XOFF1 6 /* Xoff1 Character Register */
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#define SB105X_XOFF2 7 /* Xoff2 Character Register */
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/*
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* ******************************************************************
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* * LCR = 0xBF, PSR[0] = 1 ============ Page 4 Registers *
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* ******************************************************************
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*/
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#define SB105X_AFR 1 /* Additional Feature Register */
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#define SB105X_AFR_GIPS 0x20 /* Global Interrupt Polarity Select */
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#define SB105X_AFR_GIEN 0x10 /* Global Interrupt Enable */
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#define SB105X_AFR_AFEN 0x01 /* 256-byte FIFO Enable */
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#define SB105X_XRCR 2 /* Xoff Re-transmit Count Register */
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#define SB105X_XRCR_NRC1 0x00 /* Transmits Xoff Character whenever the number of received data is 1 during XOFF status */
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#define SB105X_XRCR_NRC4 0x01 /* Transmits Xoff Character whenever the number of received data is 4 during XOFF status */
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#define SB105X_XRCR_NRC8 0x02 /* Transmits Xoff Character whenever the number of received data is 8 during XOFF status */
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#define SB105X_XRCR_NRC16 0x03 /* Transmits Xoff Character whenever the number of received data is 16 during XOFF status */
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#define SB105X_TTR 4 /* Transmit FIFO Trigger Level Register */
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#define SB105X_RTR 5 /* Receive FIFO Trigger Level Register */
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#define SB105X_FUR 6 /* Flow Control Upper Threshold Register */
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#define SB105X_FLR 7 /* Flow Control Lower Threshold Register */
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/* page 0 */
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#define SB105X_GET_CHAR(port) inb((port)->iobase + SB105X_RX)
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#define SB105X_GET_IER(port) inb((port)->iobase + SB105X_IER)
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#define SB105X_GET_ISR(port) inb((port)->iobase + SB105X_ISR)
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#define SB105X_GET_LCR(port) inb((port)->iobase + SB105X_LCR)
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#define SB105X_GET_MCR(port) inb((port)->iobase + SB105X_MCR)
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#define SB105X_GET_LSR(port) inb((port)->iobase + SB105X_LSR)
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#define SB105X_GET_MSR(port) inb((port)->iobase + SB105X_MSR)
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#define SB105X_GET_SPR(port) inb((port)->iobase + SB105X_SPR)
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#define SB105X_PUT_CHAR(port,v) outb((v),(port)->iobase + SB105X_TX )
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#define SB105X_PUT_IER(port,v) outb((v),(port)->iobase + SB105X_IER )
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#define SB105X_PUT_FCR(port,v) outb((v),(port)->iobase + SB105X_FCR )
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#define SB105X_PUT_LCR(port,v) outb((v),(port)->iobase + SB105X_LCR )
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#define SB105X_PUT_MCR(port,v) outb((v),(port)->iobase + SB105X_MCR )
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#define SB105X_PUT_SPR(port,v) outb((v),(port)->iobase + SB105X_SPR )
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/* page 1 */
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#define SB105X_GET_REG(port,reg) inb((port)->iobase + (reg))
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#define SB105X_PUT_REG(port,reg,v) outb((v),(port)->iobase + (reg))
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/* page 2 */
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#define SB105X_PUT_PSR(port,v) outb((v),(port)->iobase + SB105X_PSR )
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#endif
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File diff suppressed because it is too large
Load Diff
@ -1,291 +0,0 @@
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial.h>
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#include <linux/serial_reg.h>
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#include <linux/ioport.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include <linux/tty_driver.h>
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#include <linux/pci.h>
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#include <linux/circ_buf.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/serial.h>
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#include <linux/interrupt.h>
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#include <linux/parport.h>
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#include <linux/ctype.h>
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#include <linux/poll.h>
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#define MP_TERMIOS ktermios
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#include "sb_mp_register.h"
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#include "sb_ser_core.h"
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#define DRIVER_VERSION "1.1"
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#define DRIVER_DATE "2012/01/05"
|
||||
#define DRIVER_AUTHOR "SYSTEMBASE<tech@sysbas.com>"
|
||||
#define DRIVER_DESC "SystemBase PCI/PCIe Multiport Core"
|
||||
|
||||
#define SB_TTY_MP_MAJOR 54
|
||||
#define PCI_VENDOR_ID_MULTIPORT 0x14A1
|
||||
|
||||
#define PCI_DEVICE_ID_MP1 0x4d01
|
||||
#define PCI_DEVICE_ID_MP2 0x4d02
|
||||
#define PCI_DEVICE_ID_MP4 0x4d04
|
||||
#define PCI_DEVICE_ID_MP4A 0x4d54
|
||||
#define PCI_DEVICE_ID_MP6 0x4d06
|
||||
#define PCI_DEVICE_ID_MP6A 0x4d56
|
||||
#define PCI_DEVICE_ID_MP8 0x4d08
|
||||
#define PCI_DEVICE_ID_MP32 0x4d32
|
||||
/* Parallel port */
|
||||
#define PCI_DEVICE_ID_MP1P 0x4301
|
||||
#define PCI_DEVICE_ID_MP2S1P 0x4303
|
||||
|
||||
#define PCIE_DEVICE_ID_MP1 0x4501
|
||||
#define PCIE_DEVICE_ID_MP2 0x4502
|
||||
#define PCIE_DEVICE_ID_MP4 0x4504
|
||||
#define PCIE_DEVICE_ID_MP8 0x4508
|
||||
#define PCIE_DEVICE_ID_MP32 0x4532
|
||||
|
||||
#define PCIE_DEVICE_ID_MP1E 0x4e01
|
||||
#define PCIE_DEVICE_ID_MP2E 0x4e02
|
||||
#define PCIE_DEVICE_ID_MP2B 0x4b02
|
||||
#define PCIE_DEVICE_ID_MP4B 0x4b04
|
||||
#define PCIE_DEVICE_ID_MP8B 0x4b08
|
||||
|
||||
#define PCI_DEVICE_ID_GT_MP4 0x0004
|
||||
#define PCI_DEVICE_ID_GT_MP4A 0x0054
|
||||
#define PCI_DEVICE_ID_GT_MP6 0x0006
|
||||
#define PCI_DEVICE_ID_GT_MP6A 0x0056
|
||||
#define PCI_DEVICE_ID_GT_MP8 0x0008
|
||||
#define PCI_DEVICE_ID_GT_MP32 0x0032
|
||||
|
||||
#define PCIE_DEVICE_ID_GT_MP1 0x1501
|
||||
#define PCIE_DEVICE_ID_GT_MP2 0x1502
|
||||
#define PCIE_DEVICE_ID_GT_MP4 0x1504
|
||||
#define PCIE_DEVICE_ID_GT_MP8 0x1508
|
||||
#define PCIE_DEVICE_ID_GT_MP32 0x1532
|
||||
|
||||
#define PCI_DEVICE_ID_MP4M 0x4604 //modem
|
||||
|
||||
#define MAX_MP_DEV 8
|
||||
#define BD_MAX_PORT 32 /* Max serial port in one board */
|
||||
#define MAX_MP_PORT 256 /* Max serial port in one PC */
|
||||
|
||||
#define PORT_16C105XA 3
|
||||
#define PORT_16C105X 2
|
||||
#define PORT_16C55X 1
|
||||
|
||||
#define ENABLE 1
|
||||
#define DISABLE 0
|
||||
|
||||
/* ioctls */
|
||||
#define TIOCGNUMOFPORT 0x545F
|
||||
#define TIOCSMULTIECHO 0x5440
|
||||
#define TIOCSPTPNOECHO 0x5441
|
||||
|
||||
#define TIOCGOPTIONREG 0x5461
|
||||
#define TIOCGDISABLEIRQ 0x5462
|
||||
#define TIOCGENABLEIRQ 0x5463
|
||||
#define TIOCGSOFTRESET 0x5464
|
||||
#define TIOCGSOFTRESETR 0x5465
|
||||
#define TIOCGREGINFO 0x5466
|
||||
#define TIOCGGETLSR 0x5467
|
||||
#define TIOCGGETDEVID 0x5468
|
||||
#define TIOCGGETBDNO 0x5469
|
||||
#define TIOCGGETINTERFACE 0x546A
|
||||
#define TIOCGGETREV 0x546B
|
||||
#define TIOCGGETNRPORTS 0x546C
|
||||
#define TIOCGGETPORTTYPE 0x546D
|
||||
#define GETDEEPFIFO 0x54AA
|
||||
#define SETDEEPFIFO 0x54AB
|
||||
#define SETFCR 0x54BA
|
||||
#define SETTTR 0x54B1
|
||||
#define SETRTR 0x54B2
|
||||
#define GETTTR 0x54B3
|
||||
#define GETRTR 0x54B4
|
||||
|
||||
/* multi-drop mode related ioctl commands */
|
||||
#define TIOCSMULTIDROP 0x5470
|
||||
#define TIOCSMDADDR 0x5471
|
||||
#define TIOCGMDADDR 0x5472
|
||||
#define TIOCSENDADDR 0x5473
|
||||
|
||||
|
||||
/* serial interface */
|
||||
#define RS232 1
|
||||
#define RS422PTP 2
|
||||
#define RS422MD 3
|
||||
#define RS485NE 4
|
||||
#define RS485ECHO 5
|
||||
|
||||
#define serial_inp(up, offset) serial_in(up, offset)
|
||||
#define serial_outp(up, offset, value) serial_out(up, offset, value)
|
||||
|
||||
#define PASS_LIMIT 256
|
||||
#define is_real_interrupt(irq) ((irq) != 0)
|
||||
|
||||
#define PROBE_ANY (~0)
|
||||
|
||||
static DEFINE_MUTEX(mp_mutex);
|
||||
#define MP_MUTEX_LOCK(x) mutex_lock(&(x))
|
||||
#define MP_MUTEX_UNLOCK(x) mutex_unlock(&(x))
|
||||
#define MP_STATE_LOCK(x) mutex_lock(&((x)->mutex))
|
||||
#define MP_STATE_UNLOCK(x) mutex_unlock(&((x)->mutex))
|
||||
|
||||
|
||||
#define UART_LSR_SPECIAL 0x1E
|
||||
|
||||
#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
|
||||
#define uart_users(state) ((state)->count + ((state)->info ? (state)->info->blocked_open : 0))
|
||||
|
||||
|
||||
//#define MP_DEBUG 1
|
||||
#undef MP_DEBUG
|
||||
|
||||
#ifdef MP_DEBUG
|
||||
#define DPRINTK(x...) printk(x)
|
||||
#else
|
||||
#define DPRINTK(x...) do { } while (0)
|
||||
#endif
|
||||
|
||||
#ifdef MP_DEBUG
|
||||
#define DEBUG_AUTOCONF(fmt...) printk(fmt)
|
||||
#else
|
||||
#define DEBUG_AUTOCONF(fmt...) do { } while (0)
|
||||
#endif
|
||||
|
||||
#ifdef MP_DEBUG
|
||||
#define DEBUG_INTR(fmt...) printk(fmt)
|
||||
#else
|
||||
#define DEBUG_INTR(fmt...) do { } while (0)
|
||||
#endif
|
||||
|
||||
#if defined(__i386__) && defined(CONFIG_M486)
|
||||
#define SERIAL_INLINE
|
||||
#endif
|
||||
#ifdef SERIAL_INLINE
|
||||
#define _INLINE_ inline
|
||||
#else
|
||||
#define _INLINE_
|
||||
#endif
|
||||
|
||||
#define TYPE_POLL 1
|
||||
#define TYPE_INTERRUPT 2
|
||||
|
||||
|
||||
struct mp_device_t {
|
||||
unsigned short device_id;
|
||||
unsigned char revision;
|
||||
char *name;
|
||||
unsigned long uart_access_addr;
|
||||
unsigned long option_reg_addr;
|
||||
unsigned long reserved_addr[4];
|
||||
int irq;
|
||||
int nr_ports;
|
||||
int poll_type;
|
||||
};
|
||||
|
||||
typedef struct mppcibrd {
|
||||
char *name;
|
||||
unsigned short vendor_id;
|
||||
unsigned short device_id;
|
||||
} mppcibrd_t;
|
||||
|
||||
static mppcibrd_t mp_pciboards[] = {
|
||||
|
||||
{ "Multi-1 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP1} ,
|
||||
{ "Multi-2 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP2} ,
|
||||
{ "Multi-4 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4} ,
|
||||
{ "Multi-4 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4A} ,
|
||||
{ "Multi-6 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP6} ,
|
||||
{ "Multi-6 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP6A} ,
|
||||
{ "Multi-8 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP8} ,
|
||||
{ "Multi-32 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP32} ,
|
||||
|
||||
{ "Multi-1P PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP1P} ,
|
||||
{ "Multi-2S1P PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP2S1P} ,
|
||||
|
||||
{ "Multi-4(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP4} ,
|
||||
{ "Multi-4(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP4A} ,
|
||||
{ "Multi-6(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP6} ,
|
||||
{ "Multi-6(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP6A} ,
|
||||
{ "Multi-8(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP8} ,
|
||||
{ "Multi-32(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP32} ,
|
||||
|
||||
{ "Multi-1 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP1} ,
|
||||
{ "Multi-2 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2} ,
|
||||
{ "Multi-4 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP4} ,
|
||||
{ "Multi-8 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP8} ,
|
||||
{ "Multi-32 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP32} ,
|
||||
|
||||
{ "Multi-1 PCIe E", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP1E} ,
|
||||
{ "Multi-2 PCIe E", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2E} ,
|
||||
{ "Multi-2 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2B} ,
|
||||
{ "Multi-4 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP4B} ,
|
||||
{ "Multi-8 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP8B} ,
|
||||
|
||||
{ "Multi-1(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP1} ,
|
||||
{ "Multi-2(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP2} ,
|
||||
{ "Multi-4(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP4} ,
|
||||
{ "Multi-8(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP8} ,
|
||||
{ "Multi-32(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP32} ,
|
||||
|
||||
{ "Multi-4M PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4M} ,
|
||||
};
|
||||
|
||||
struct mp_port {
|
||||
struct sb_uart_port port;
|
||||
|
||||
struct timer_list timer; /* "no irq" timer */
|
||||
struct list_head list; /* ports on this IRQ */
|
||||
unsigned int capabilities; /* port capabilities */
|
||||
unsigned short rev;
|
||||
unsigned char acr;
|
||||
unsigned char ier;
|
||||
unsigned char lcr;
|
||||
unsigned char mcr;
|
||||
unsigned char mcr_mask; /* mask of user bits */
|
||||
unsigned char mcr_force; /* mask of forced bits */
|
||||
unsigned char lsr_break_flag;
|
||||
|
||||
void (*pm)(struct sb_uart_port *port,
|
||||
unsigned int state, unsigned int old);
|
||||
struct mp_device_t *device;
|
||||
unsigned long interface_config_addr;
|
||||
unsigned long option_base_addr;
|
||||
unsigned char interface;
|
||||
unsigned char poll_type;
|
||||
};
|
||||
|
||||
struct irq_info {
|
||||
spinlock_t lock;
|
||||
struct list_head *head;
|
||||
};
|
||||
|
||||
struct sb105x_uart_config {
|
||||
char *name;
|
||||
int dfl_xmit_fifo_size;
|
||||
int flags;
|
||||
};
|
||||
|
||||
static const struct sb105x_uart_config uart_config[] = {
|
||||
{ "unknown", 1, 0 },
|
||||
{ "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
|
||||
{ "SB16C1050", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
|
||||
{ "SB16C1050A", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -1,368 +0,0 @@
|
||||
#include <linux/wait.h>
|
||||
|
||||
#define UART_CONFIG_TYPE (1 << 0)
|
||||
#define UART_CONFIG_IRQ (1 << 1)
|
||||
#define UPIO_PORT (0)
|
||||
#define UPIO_HUB6 (1)
|
||||
#define UPIO_MEM (2)
|
||||
#define UPIO_MEM32 (3)
|
||||
#define UPIO_AU (4) /* Au1x00 type IO */
|
||||
#define UPIO_TSI (5) /* Tsi108/109 type IO */
|
||||
#define UPF_FOURPORT (1 << 1)
|
||||
#define UPF_SAK (1 << 2)
|
||||
#define UPF_SPD_MASK (0x1030)
|
||||
#define UPF_SPD_HI (0x0010)
|
||||
#define UPF_SPD_VHI (0x0020)
|
||||
#define UPF_SPD_CUST (0x0030)
|
||||
#define UPF_SPD_SHI (0x1000)
|
||||
#define UPF_SPD_WARP (0x1010)
|
||||
#define UPF_SKIP_TEST (1 << 6)
|
||||
#define UPF_AUTO_IRQ (1 << 7)
|
||||
#define UPF_HARDPPS_CD (1 << 11)
|
||||
#define UPF_LOW_LATENCY (1 << 13)
|
||||
#define UPF_BUGGY_UART (1 << 14)
|
||||
#define UPF_MAGIC_MULTIPLIER (1 << 16)
|
||||
#define UPF_CONS_FLOW (1 << 23)
|
||||
#define UPF_SHARE_IRQ (1 << 24)
|
||||
#define UPF_BOOT_AUTOCONF (1 << 28)
|
||||
#define UPF_DEAD (1 << 30)
|
||||
#define UPF_IOREMAP (1 << 31)
|
||||
#define UPF_CHANGE_MASK (0x17fff)
|
||||
#define UPF_USR_MASK (UPF_SPD_MASK|UPF_LOW_LATENCY)
|
||||
#define USF_CLOSING_WAIT_INF (0)
|
||||
#define USF_CLOSING_WAIT_NONE (~0U)
|
||||
|
||||
#define UART_XMIT_SIZE PAGE_SIZE
|
||||
|
||||
#define UIF_CHECK_CD (1 << 25)
|
||||
#define UIF_CTS_FLOW (1 << 26)
|
||||
#define UIF_NORMAL_ACTIVE (1 << 29)
|
||||
#define UIF_INITIALIZED (1 << 31)
|
||||
#define UIF_SUSPENDED (1 << 30)
|
||||
|
||||
#define WAKEUP_CHARS 256
|
||||
|
||||
#define uart_circ_empty(circ) ((circ)->head == (circ)->tail)
|
||||
#define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0)
|
||||
|
||||
#define uart_circ_chars_pending(circ) \
|
||||
(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))
|
||||
|
||||
#define uart_circ_chars_free(circ) \
|
||||
(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))
|
||||
|
||||
#define uart_tx_stopped(port) \
|
||||
((port)->info->tty->stopped || (port)->info->tty->hw_stopped)
|
||||
|
||||
#define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD || \
|
||||
(cflag) & CRTSCTS || \
|
||||
!((cflag) & CLOCAL))
|
||||
|
||||
|
||||
struct sb_uart_port;
|
||||
struct sb_uart_info;
|
||||
struct serial_struct;
|
||||
struct device;
|
||||
|
||||
struct sb_uart_ops {
|
||||
unsigned int (*tx_empty)(struct sb_uart_port *);
|
||||
void (*set_mctrl)(struct sb_uart_port *, unsigned int mctrl);
|
||||
unsigned int (*get_mctrl)(struct sb_uart_port *);
|
||||
void (*stop_tx)(struct sb_uart_port *);
|
||||
void (*start_tx)(struct sb_uart_port *);
|
||||
void (*send_xchar)(struct sb_uart_port *, char ch);
|
||||
void (*stop_rx)(struct sb_uart_port *);
|
||||
void (*enable_ms)(struct sb_uart_port *);
|
||||
void (*break_ctl)(struct sb_uart_port *, int ctl);
|
||||
int (*startup)(struct sb_uart_port *);
|
||||
void (*shutdown)(struct sb_uart_port *);
|
||||
void (*set_termios)(struct sb_uart_port *, struct MP_TERMIOS *new,
|
||||
struct MP_TERMIOS *old);
|
||||
void (*pm)(struct sb_uart_port *, unsigned int state,
|
||||
unsigned int oldstate);
|
||||
int (*set_wake)(struct sb_uart_port *, unsigned int state);
|
||||
|
||||
const char *(*type)(struct sb_uart_port *);
|
||||
|
||||
void (*release_port)(struct sb_uart_port *);
|
||||
|
||||
int (*request_port)(struct sb_uart_port *);
|
||||
void (*config_port)(struct sb_uart_port *, int);
|
||||
int (*verify_port)(struct sb_uart_port *, struct serial_struct *);
|
||||
int (*ioctl)(struct sb_uart_port *, unsigned int, unsigned long);
|
||||
};
|
||||
|
||||
|
||||
struct sb_uart_icount {
|
||||
__u32 cts;
|
||||
__u32 dsr;
|
||||
__u32 rng;
|
||||
__u32 dcd;
|
||||
__u32 rx;
|
||||
__u32 tx;
|
||||
__u32 frame;
|
||||
__u32 overrun;
|
||||
__u32 parity;
|
||||
__u32 brk;
|
||||
__u32 buf_overrun;
|
||||
};
|
||||
typedef unsigned int upf_t;
|
||||
|
||||
struct sb_uart_port {
|
||||
spinlock_t lock; /* port lock */
|
||||
unsigned int iobase; /* in/out[bwl] */
|
||||
unsigned char __iomem *membase; /* read/write[bwl] */
|
||||
unsigned int irq; /* irq number */
|
||||
unsigned int uartclk; /* base uart clock */
|
||||
unsigned int fifosize; /* tx fifo size */
|
||||
unsigned char x_char; /* xon/xoff char */
|
||||
unsigned char regshift; /* reg offset shift */
|
||||
unsigned char iotype; /* io access style */
|
||||
unsigned char unused1;
|
||||
|
||||
|
||||
unsigned int read_status_mask; /* driver specific */
|
||||
unsigned int ignore_status_mask; /* driver specific */
|
||||
struct sb_uart_info *info; /* pointer to parent info */
|
||||
struct sb_uart_icount icount; /* statistics */
|
||||
|
||||
struct console *cons; /* struct console, if any */
|
||||
#ifdef CONFIG_SERIAL_CORE_CONSOLE
|
||||
unsigned long sysrq; /* sysrq timeout */
|
||||
#endif
|
||||
|
||||
upf_t flags;
|
||||
|
||||
unsigned int mctrl; /* current modem ctrl settings */
|
||||
unsigned int timeout; /* character-based timeout */
|
||||
unsigned int type; /* port type */
|
||||
const struct sb_uart_ops *ops;
|
||||
unsigned int custom_divisor;
|
||||
unsigned int line; /* port index */
|
||||
unsigned long mapbase; /* for ioremap */
|
||||
struct device *dev; /* parent device */
|
||||
unsigned char hub6; /* this should be in the 8250 driver */
|
||||
unsigned char unused[3];
|
||||
};
|
||||
|
||||
#define mdmode unused[2]
|
||||
#define MDMODE_ADDR 0x1
|
||||
#define MDMODE_ENABLE 0x2
|
||||
#define MDMODE_AUTO 0x4
|
||||
#define MDMODE_ADDRSEND 0x8
|
||||
|
||||
struct sb_uart_state {
|
||||
unsigned int close_delay; /* msec */
|
||||
unsigned int closing_wait; /* msec */
|
||||
|
||||
|
||||
int count;
|
||||
int pm_state;
|
||||
struct sb_uart_info *info;
|
||||
struct sb_uart_port *port;
|
||||
|
||||
struct mutex mutex;
|
||||
};
|
||||
|
||||
typedef unsigned int uif_t;
|
||||
|
||||
struct sb_uart_info {
|
||||
struct tty_struct *tty;
|
||||
struct circ_buf xmit;
|
||||
uif_t flags;
|
||||
|
||||
int blocked_open;
|
||||
|
||||
struct tasklet_struct tlet;
|
||||
|
||||
wait_queue_head_t open_wait;
|
||||
wait_queue_head_t delta_msr_wait;
|
||||
};
|
||||
|
||||
|
||||
struct module;
|
||||
struct tty_driver;
|
||||
|
||||
struct uart_driver {
|
||||
struct module *owner;
|
||||
const char *driver_name;
|
||||
const char *dev_name;
|
||||
int major;
|
||||
int minor;
|
||||
int nr;
|
||||
struct console *cons;
|
||||
|
||||
struct sb_uart_state *state;
|
||||
struct tty_driver *tty_driver;
|
||||
};
|
||||
|
||||
void sb_uart_write_wakeup(struct sb_uart_port *port)
|
||||
{
|
||||
struct sb_uart_info *info = port->info;
|
||||
tasklet_schedule(&info->tlet);
|
||||
}
|
||||
|
||||
void sb_uart_update_timeout(struct sb_uart_port *port, unsigned int cflag,
|
||||
unsigned int baud)
|
||||
{
|
||||
unsigned int bits;
|
||||
|
||||
switch (cflag & CSIZE)
|
||||
{
|
||||
case CS5:
|
||||
bits = 7;
|
||||
break;
|
||||
|
||||
case CS6:
|
||||
bits = 8;
|
||||
break;
|
||||
|
||||
case CS7:
|
||||
bits = 9;
|
||||
break;
|
||||
|
||||
default:
|
||||
bits = 10;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cflag & CSTOPB)
|
||||
{
|
||||
bits++;
|
||||
}
|
||||
|
||||
if (cflag & PARENB)
|
||||
{
|
||||
bits++;
|
||||
}
|
||||
|
||||
bits = bits * port->fifosize;
|
||||
|
||||
port->timeout = (HZ * bits) / baud + HZ/50;
|
||||
}
|
||||
unsigned int sb_uart_get_baud_rate(struct sb_uart_port *port, struct MP_TERMIOS *termios,
|
||||
struct MP_TERMIOS *old, unsigned int min,
|
||||
unsigned int max)
|
||||
{
|
||||
unsigned int try, baud, altbaud = 38400;
|
||||
upf_t flags = port->flags & UPF_SPD_MASK;
|
||||
|
||||
if (flags == UPF_SPD_HI)
|
||||
altbaud = 57600;
|
||||
if (flags == UPF_SPD_VHI)
|
||||
altbaud = 115200;
|
||||
if (flags == UPF_SPD_SHI)
|
||||
altbaud = 230400;
|
||||
if (flags == UPF_SPD_WARP)
|
||||
altbaud = 460800;
|
||||
|
||||
for (try = 0; try < 2; try++) {
|
||||
|
||||
switch (termios->c_cflag & (CBAUD | CBAUDEX))
|
||||
{
|
||||
case B921600 : baud = 921600; break;
|
||||
case B460800 : baud = 460800; break;
|
||||
case B230400 : baud = 230400; break;
|
||||
case B115200 : baud = 115200; break;
|
||||
case B57600 : baud = 57600; break;
|
||||
case B38400 : baud = 38400; break;
|
||||
case B19200 : baud = 19200; break;
|
||||
case B9600 : baud = 9600; break;
|
||||
case B4800 : baud = 4800; break;
|
||||
case B2400 : baud = 2400; break;
|
||||
case B1800 : baud = 1800; break;
|
||||
case B1200 : baud = 1200; break;
|
||||
case B600 : baud = 600; break;
|
||||
case B300 : baud = 300; break;
|
||||
case B200 : baud = 200; break;
|
||||
case B150 : baud = 150; break;
|
||||
case B134 : baud = 134; break;
|
||||
case B110 : baud = 110; break;
|
||||
case B75 : baud = 75; break;
|
||||
case B50 : baud = 50; break;
|
||||
default : baud = 9600; break;
|
||||
}
|
||||
|
||||
if (baud == 38400)
|
||||
baud = altbaud;
|
||||
|
||||
if (baud == 0)
|
||||
baud = 9600;
|
||||
|
||||
if (baud >= min && baud <= max)
|
||||
return baud;
|
||||
|
||||
termios->c_cflag &= ~CBAUD;
|
||||
if (old) {
|
||||
termios->c_cflag |= old->c_cflag & CBAUD;
|
||||
old = NULL;
|
||||
continue;
|
||||
}
|
||||
|
||||
termios->c_cflag |= B9600;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
unsigned int sb_uart_get_divisor(struct sb_uart_port *port, unsigned int baud)
|
||||
{
|
||||
unsigned int quot;
|
||||
|
||||
if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
|
||||
quot = port->custom_divisor;
|
||||
else
|
||||
quot = (port->uartclk + (8 * baud)) / (16 * baud);
|
||||
|
||||
return quot;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static inline int sb_uart_handle_break(struct sb_uart_port *port)
|
||||
{
|
||||
struct sb_uart_info *info = port->info;
|
||||
|
||||
if (port->flags & UPF_SAK)
|
||||
do_SAK(info->tty);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void sb_uart_handle_dcd_change(struct sb_uart_port *port, unsigned int status)
|
||||
{
|
||||
struct sb_uart_info *info = port->info;
|
||||
|
||||
port->icount.dcd++;
|
||||
|
||||
if (info->flags & UIF_CHECK_CD) {
|
||||
if (status)
|
||||
wake_up_interruptible(&info->open_wait);
|
||||
else if (info->tty)
|
||||
tty_hangup(info->tty);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void sb_uart_handle_cts_change(struct sb_uart_port *port, unsigned int status)
|
||||
{
|
||||
struct sb_uart_info *info = port->info;
|
||||
struct tty_struct *tty = info->tty;
|
||||
|
||||
port->icount.cts++;
|
||||
|
||||
if (info->flags & UIF_CTS_FLOW) {
|
||||
if (tty->hw_stopped) {
|
||||
if (status) {
|
||||
tty->hw_stopped = 0;
|
||||
port->ops->start_tx(port);
|
||||
sb_uart_write_wakeup(port);
|
||||
}
|
||||
} else {
|
||||
if (!status) {
|
||||
tty->hw_stopped = 1;
|
||||
port->ops->stop_tx(port);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user