drm/amd/display: add dcn21 core DC changes
Add missing parameters, to make dcn21 compile without errors Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -385,6 +385,9 @@ struct dc_debug_options {
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struct dc_bw_validation_profile bw_val_profile;
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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bool disable_fec;
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#endif
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#ifdef CONFIG_DRM_AMD_DC_DCN2_1
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bool disable_48mhz_pwrdwn;
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#endif
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/* This forces a hard min on the DCFCLK requested to SMU/PP
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* watermarks are not affected.
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@ -87,6 +87,9 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
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struct resource_pool;
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struct dc_state;
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struct resource_context;
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#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
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struct clk_bw_params;
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#endif
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struct resource_funcs {
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void (*destroy)(struct resource_pool **pool);
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@ -40,6 +40,10 @@ struct cstate_pstate_watermarks_st {
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struct dcn_watermarks {
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uint32_t pte_meta_urgent_ns;
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uint32_t urgent_ns;
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#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
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uint32_t frac_urg_bw_nom;
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uint32_t frac_urg_bw_flip;
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#endif
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struct cstate_pstate_watermarks_st cstate_pstate;
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};
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@ -48,6 +48,7 @@ struct dce_hwseq_wa {
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bool DEGVIDCN10_253;
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bool false_optc_underflow;
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bool DEGVIDCN10_254;
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bool DEGVIDCN21;
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};
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struct hwseq_wa_state {
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