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Merge branch 'net-mscc-miim-add-integrated-phy-reset-support'

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Michael Walle says:

====================
net: mscc-miim: add integrated PHY reset support

The MDIO driver has support to release the integrated PHYs from reset.
This was implemented for the SparX-5 for now. Now add support for the
LAN966x, too.
====================

Link: https://lore.kernel.org/r/20220318201324.1647416-1-michael@walle.cc
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2022-03-21 22:33:04 -07:00
commit aa80511a93
2 changed files with 50 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/net/mscc-miim.txt
View File

@ -2,7 +2,7 @@ Microsemi MII Management Controller (MIIM) / MDIO
=================================================
Properties:
- compatible: must be "mscc,ocelot-miim"
- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim"
- reg: The base address of the MDIO bus controller register bank. Optionally, a
second register bank can be defined if there is an associated reset register
for internal PHYs

67
drivers/net/mdio/mdio-mscc-miim.c
View File

@ -15,6 +15,7 @@
#include <linux/of_mdio.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#define MSCC_MIIM_REG_STATUS 0x0
@ -36,11 +37,19 @@
#define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8))
#define MSCC_PHY_REG_PHY_STATUS 0x4
#define LAN966X_CUPHY_COMMON_CFG 0x0
#define CUPHY_COMMON_CFG_RESET_N BIT(0)
struct mscc_miim_info {
unsigned int phy_reset_offset;
unsigned int phy_reset_bits;
};
struct mscc_miim_dev {
struct regmap *regs;
int mii_status_offset;
struct regmap *phy_regs;
int phy_reset_offset;
const struct mscc_miim_info *info;
};
/* When high resolution timers aren't built-in: we can't use usleep_range() as
@ -157,27 +166,29 @@ out:
static int mscc_miim_reset(struct mii_bus *bus)
{
struct mscc_miim_dev *miim = bus->priv;
int offset = miim->phy_reset_offset;
unsigned int offset, bits;
int ret;
if (miim->phy_regs) {
ret = regmap_write(miim->phy_regs,
MSCC_PHY_REG_PHY_CFG + offset, 0);
if (ret < 0) {
WARN_ONCE(1, "mscc reset set error %d\n", ret);
return ret;
}
if (!miim->phy_regs)
return 0;
ret = regmap_write(miim->phy_regs,
MSCC_PHY_REG_PHY_CFG + offset, 0x1ff);
if (ret < 0) {
WARN_ONCE(1, "mscc reset clear error %d\n", ret);
return ret;
}
offset = miim->info->phy_reset_offset;
bits = miim->info->phy_reset_bits;
mdelay(500);
ret = regmap_update_bits(miim->phy_regs, offset, bits, 0);
if (ret < 0) {
WARN_ONCE(1, "mscc reset set error %d\n", ret);
return ret;
}
ret = regmap_update_bits(miim->phy_regs, offset, bits, bits);
if (ret < 0) {
WARN_ONCE(1, "mscc reset clear error %d\n", ret);
return ret;
}
mdelay(500);
return 0;
}
@ -272,7 +283,10 @@ static int mscc_miim_probe(struct platform_device *pdev)
miim = bus->priv;
miim->phy_regs = phy_regmap;
miim->phy_reset_offset = 0;
miim->info = device_get_match_data(&pdev->dev);
if (!miim->info)
return -EINVAL;
ret = of_mdiobus_register(bus, pdev->dev.of_node);
if (ret < 0) {
@ -294,8 +308,25 @@ static int mscc_miim_remove(struct platform_device *pdev)
return 0;
}
static const struct mscc_miim_info mscc_ocelot_miim_info = {
.phy_reset_offset = MSCC_PHY_REG_PHY_CFG,
.phy_reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET |
PHY_CFG_PHY_RESET,
};
static const struct mscc_miim_info microchip_lan966x_miim_info = {
.phy_reset_offset = LAN966X_CUPHY_COMMON_CFG,
.phy_reset_bits = CUPHY_COMMON_CFG_RESET_N,
};
static const struct of_device_id mscc_miim_match[] = {
{ .compatible = "mscc,ocelot-miim" },
{
.compatible = "mscc,ocelot-miim",
.data = &mscc_ocelot_miim_info
}, {
.compatible = "microchip,lan966x-miim",
.data = &microchip_lan966x_miim_info
},
{ }
};
MODULE_DEVICE_TABLE(of, mscc_miim_match);