From 79bd11db8ba8046943dddf740d58baac54326f56 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 20 Sep 2020 21:57:49 +0200 Subject: [PATCH 01/40] ARM: dts: imx: align GPIO hog names with dtschema dtschema for GPIO controllers expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 2 +- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 8 ++++---- arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index e559ab0c3645..ec8ca3ac2c1c 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -451,7 +451,7 @@ "", "", "", "", "", "", "", ""; - unused-sd3-wp-gpio { + unused-sd3-wp-hog { /* * See pinctrl_esdhc1 below for more details on this */ diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 66b15748e287..c0a76202e16b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -330,28 +330,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio3_hog>; - usb-emulation { + usb-emulation-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_HIGH>; output-low; line-name = "usb-emulation"; }; - usb-mode1 { + usb-mode1-hog { gpio-hog; gpios = <20 GPIO_ACTIVE_HIGH>; output-high; line-name = "usb-mode1"; }; - usb-pwr { + usb-pwr-hog { gpio-hog; gpios = <22 GPIO_ACTIVE_LOW>; output-high; line-name = "usb-pwr-ctrl-en-n"; }; - usb-mode2 { + usb-mode2-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts index a0bbec57ddc7..3ec042bfccba 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts @@ -110,7 +110,7 @@ }; &gpio5 { - emmc-usd-mux { + emmc-usd-mux-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_LOW>; output-high; From faa3b6dfd2527eace517e0cd1b147154c780d582 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 28 Aug 2020 21:33:02 +0530 Subject: [PATCH 02/40] ARM: dts: imx6q-icore-ofcap10: Use 10.1" Ampire panel compatible Adding display timings directly on device tree files make it difficult to maintain as a same copy of timings may exist on different files or panel-simple driver. We have a panel-simple driver for this particular usage so supporting on this driver will help to use the same timings on any device tree files if the board mounted on a similar vendor display. Engicam C.TOUCH OF 10.1" LCD board uses Ampire 10.1" TFT LCD and it has supported by panel-simple already, so simply use that binding. Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-icore-ofcap10.dts | 28 +++++++++++++---------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts index 81cc346dd149..02aca1e28ce3 100644 --- a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts +++ b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts @@ -12,6 +12,17 @@ / { model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit"; compatible = "engicam,imx6-icore", "fsl,imx6q"; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; }; &ldb { @@ -22,18 +33,11 @@ fsl,data-width = <24>; status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <10>; - vfront-porch = <3>; - hsync-len = <80>; - vsync-len = <10>; + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; From 68e680c5faddb207ac4ebb50c88bcc88284bcd5f Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:32 +0200 Subject: [PATCH 03/40] ARM: dts: imx7-mba7: update compatible strings Include the SoM compatible string. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-mba7.dts | 2 +- arch/arm/boot/dts/imx7s-mba7.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 221274c73dbd..9f4f7112e598 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -14,7 +14,7 @@ / { model = "TQ Systems TQMa7D board on MBa7 carrier board"; - compatible = "tq,imx7d-mba7", "fsl,imx7d"; + compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d"; }; &fec2 { diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/imx7s-mba7.dts index a143d566a38b..d7d3f530f843 100644 --- a/arch/arm/boot/dts/imx7s-mba7.dts +++ b/arch/arm/boot/dts/imx7s-mba7.dts @@ -14,5 +14,5 @@ / { model = "TQ Systems TQMa7S board on MBa7 carrier board"; - compatible = "tq,imx7s-mba7", "fsl,imx7s"; + compatible = "tq,imx7s-mba7", "tq,imx7s-tqma7", "fsl,imx7s"; }; From f7defed53e35fada087a6bde29810be74576b86e Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:33 +0200 Subject: [PATCH 04/40] ARM: dts: imx7-mba7: drop incorrect num-chipselects property This property was never set correctly; it should have been num-cs. As num-cs support is being removed as well, simply drop it. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 50abf18ad30b..d99912ade947 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -179,7 +179,6 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - num-chipselects = <3>; cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, <&gpio4 2 GPIO_ACTIVE_LOW>; status = "okay"; @@ -188,7 +187,6 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - num-chipselects = <1>; status = "okay"; }; From 2b01d7a1571b8558dcadee84d575ab31bf39efa2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:34 +0200 Subject: [PATCH 05/40] ARM: dts: imx7-mba7: remove unsupported PHY LED setup These properties were never supported by the DP83867, and a patch implementing them was rejected in favor of a different solution. Remove them. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 4 ---- arch/arm/boot/dts/imx7d-mba7.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index d99912ade947..1af40032ab17 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -212,10 +212,6 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; - /* LED1: Link/Activity, LED2: Error */ - ti,led-function = <0x0db0>; - /* Active low, LED1 and LED2 driven by phy */ - ti,led-ctrl = <0x1001>; }; }; }; diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 9f4f7112e598..1101be373ddf 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -39,10 +39,6 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; - /* LED1: Link/Activity, LED2: error */ - ti,led-function = <0x0db0>; - /* active low, LED1/2 driven by phy */ - ti,led-ctrl = <0x1001>; }; }; }; From e70f9b9c25eae1b1624a976773817470c51d1e9f Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:35 +0200 Subject: [PATCH 06/40] ARM: dts: imx7-mba7: disable ethernet PHY clock outputs The clock outputs are not connected. Disable them to improve EMI behaviour. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 1 + arch/arm/boot/dts/imx7d-mba7.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 1af40032ab17..9be225bb135a 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -212,6 +212,7 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; + ti,clk-output-sel = ; }; }; }; diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 1101be373ddf..5ef86de53013 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -39,6 +39,7 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; + ti,clk-output-sel = ; }; }; }; From d50765205d8e59e4116a9dc512305cef15e70ad2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:36 +0200 Subject: [PATCH 07/40] ARM: dts: imx7-mba7: configure watchdog The external watchdog reset is necessary, as the internal reset is unreliable on i.MX7. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 9be225bb135a..84b5809f384c 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -467,6 +467,12 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 >; }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; }; &pwm1 { @@ -543,3 +549,9 @@ no-1-8-v; status = "okay"; }; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; From ecb5ba9f112424ed43907cd95ddf6a5eb8c0e6fe Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:37 +0200 Subject: [PATCH 08/40] ARM: dts: imx7-mba7: update MMC aliases Together with the recently merged support for alias-based MMC host numbering, this makes the MMC devices names match what the bootloader expects. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 84b5809f384c..215730e0453e 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -14,6 +14,12 @@ #include / { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + /delete-property/ mmc2; + }; + beeper { compatible = "gpio-beeper"; gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; From 0d5e50cf30d7c6ec56013234595ddefdaba64593 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:38 +0200 Subject: [PATCH 09/40] ARM: dts: imx7-mba7: add audio support The MBa7x is equipped with a TI TLV320AIC3204 audio codec. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 38 +++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 215730e0453e..9cfaf0a91100 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -170,6 +170,20 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; }; &adc1 { @@ -363,13 +377,25 @@ >; }; - pinctrl_pca9555: pca95550grp { fsl,pins = < MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 + MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c + MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c + + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e @@ -487,6 +513,16 @@ status = "okay"; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; From 9af6702fa1e3ecdbed8c297e3c08103c2ceda112 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:40 +0200 Subject: [PATCH 10/40] ARM: dts: imx7-mba7: enable RS485 on UART7 The UART7 interface is connected to a full-duplex RS485 transceiver. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 9cfaf0a91100..ea9f0a4ac4b5 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -561,6 +561,9 @@ assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; status = "okay"; }; From b8a4f64a3277fd30b1ee04bacf03d0dd3f5ade88 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:41 +0200 Subject: [PATCH 11/40] ARM: dts: imx7-mba7: specify USB over-current polarity Add over-current-active-low to usbotg1. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index ea9f0a4ac4b5..f9704c354e1d 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -578,6 +578,7 @@ srp-disable; hnp-disable; adp-disable; + over-current-active-low; dr_mode = "host"; status = "okay"; }; From 42ab1ba8873d0b144a9417231e7b15a26b6137ad Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:42 +0200 Subject: [PATCH 12/40] ARM: dts: imx7-mba7: set dr_mode to otg on usbotg1 USBOTG1 has a Micro-USB port that can be used in host mode (using an OTG cable) or device mode. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index f9704c354e1d..c6d1c63f7905 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -579,7 +579,7 @@ hnp-disable; adp-disable; over-current-active-low; - dr_mode = "host"; + dr_mode = "otg"; status = "okay"; }; From a8d54a39e95f5cff7ba25b344cbab9b598bbf937 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:08 +0200 Subject: [PATCH 13/40] ARM: dts: imx6ul: segin: Fix stmpe touchscreen subnode name The touchscreen subnode name needs to be stmpe_touchscreen as mentioned in the dt-bindings. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index f1513e676c2f..7367279748f4 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -139,7 +139,7 @@ pinctrl-0 = <&pinctrl_stmpe>; status = "disabled"; - touchscreen { + stmpe_touchscreen { compatible = "st,stmpe-ts"; st,sample-time = <4>; st,mod-12b = <1>; From f0e24ec59076df374d4e8f15a9658e140858afb0 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:09 +0200 Subject: [PATCH 14/40] ARM: dts: imx6: phytec: Set correct eeprom compatible Set the correct EEPROM compatible for phyCORE-i.MX 6 and phyFLEX-i.MX 6, as stated in the device tree bindings. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index e361df26a168..d51852857758 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -116,7 +116,7 @@ status = "okay"; som_eeprom: eeprom@50 { - compatible = "atmel,24c32"; + compatible = "catalyst,24c32", "atmel,24c32"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index 41ebe4599e43..a3f4e8f6cc9e 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -84,7 +84,7 @@ status = "okay"; eeprom@50 { - compatible = "atmel,24c32"; + compatible = "st,24c32", "atmel,24c32"; reg = <0x50>; }; From 0d31d5a96b8c6c5914995f4352c2ab50e50a1865 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:10 +0200 Subject: [PATCH 15/40] ARM: dts: imx6: phytec: Add eeprom pagesize Defining the EEPROM pagesize can increase the write speed significantly. Set it to the pagesize stated in the EEPROM's datasheet for phyCORE-i.MX 6UL, phyCORE-i.MX 6 and phyFLEX-i.MX 6. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 1 + arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 1 + arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index d51852857758..7a1e53195785 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -117,6 +117,7 @@ som_eeprom: eeprom@50 { compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index a3f4e8f6cc9e..a80aa08a37cb 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -85,6 +85,7 @@ eeprom@50 { compatible = "st,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi index 88f631c8fabb..19a062635ff6 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi @@ -75,6 +75,7 @@ eeprom@52 { compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x52>; }; }; From cec12cd8d1861ad9090d0b6c70e14a4b87b1e1b4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 26 Sep 2020 18:23:01 +0200 Subject: [PATCH 16/40] ARM: dts: imx: align watchdog node name with dtschema The dtschema expects watchdog device node name to be "watchdog": arch/arm/boot/dts/imx31-bug.dt.yaml: wdog@53fdc000: $nodename:0: 'wdog@53fdc000' does not match '^watchdog(@.*|-[0-9a-f])?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- arch/arm/boot/dts/imx27.dtsi | 2 +- arch/arm/boot/dts/imx31.dtsi | 3 ++- arch/arm/boot/dts/imx35.dtsi | 2 +- arch/arm/boot/dts/imx50.dtsi | 2 +- arch/arm/boot/dts/imx51.dtsi | 4 ++-- arch/arm/boot/dts/imx53.dtsi | 4 ++-- 7 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 1ab19f1268f8..fdcca82c9986 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -525,7 +525,7 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; }; - wdog@53fdc000 { + watchdog@53fdc000 { compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 126>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 7bc132737a37..fd525c3b16fa 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -99,7 +99,7 @@ #dma-channels = <16>; }; - wdog: wdog@10002000 { + wdog: watchdog@10002000 { compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x1000>; interrupts = <27>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 45333f7e10ea..948d2a543f8d 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -315,10 +315,11 @@ clock-names = "ref", "ipg"; }; - wdog: wdog@53fdc000 { + wdog: watchdog@53fdc000 { compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 41>; + interrupts = <55>; }; pwm: pwm@53fe0000 { diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index aba16252faab..98ccc81ca6d9 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -294,7 +294,7 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; }; - wdog: wdog@53fdc000 { + wdog: watchdog@53fdc000 { compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 74>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index b6b2e6af9b96..a969f335b240 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -267,7 +267,7 @@ <&iomuxc 20 140 11>; }; - wdog1: wdog@53f98000 { + wdog1: watchdog@53f98000 { compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 985e1be03ad6..7ebb46ce9e36 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -370,14 +370,14 @@ status = "disabled"; }; - wdog1: wdog@73f98000 { + wdog1: watchdog@73f98000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; clocks = <&clks IMX5_CLK_DUMMY>; }; - wdog2: wdog@73f9c000 { + wdog2: watchdog@73f9c000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f9c000 0x4000>; interrupts = <59>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 500eeaa3a27c..000050aeeabe 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -427,14 +427,14 @@ status = "disabled"; }; - wdog1: wdog@53f98000 { + wdog1: watchdog@53f98000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; clocks = <&clks IMX5_CLK_DUMMY>; }; - wdog2: wdog@53f9c000 { + wdog2: watchdog@53f9c000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f9c000 0x4000>; interrupts = <59>; From a913e88ffb90800d531feba45025382aabf680bb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 26 Sep 2020 18:23:02 +0200 Subject: [PATCH 17/40] ARM: dts: vf: align watchdog node name with dtschema The dtschema expects watchdog device node name to be "watchdog": arch/arm/boot/dts/vf500-colibri-eval-v3.dt.yaml: wdog@4003e000: $nodename:0: 'wdog@4003e000' does not match '^watchdog(@.*|-[0-9a-f])?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vfxxx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 2259d11af721..0c8d15fd9253 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -293,7 +293,7 @@ status = "disabled"; }; - wdoga5: wdog@4003e000 { + wdoga5: watchdog@4003e000 { compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; reg = <0x4003e000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; From 5cad03883f1b96f4736027a5ee56a14e52cdfbc1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:39 +0200 Subject: [PATCH 18/40] ARM: dts: imx6dl-pico: fix board compatibles There are four flavors of TechNexion PICO-IMX6 boards. They have their own DTSes, even though in Dwarf, Nymph and Pi are exactly the same. They also have their own bindings so adjust the compatibles to match the bindings. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-pico-dwarf.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-hobbit.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-nymph.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-pi.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts index 659a8e8714ea..d85b15a8c127 100644 --- a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts +++ b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-dwarf", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts index d7403c5c4337..08fedcbcc91b 100644 --- a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-hobbit", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/imx6dl-pico-nymph.dts index b282dbf953aa..32ccfc5d41ce 100644 --- a/arch/arm/boot/dts/imx6dl-pico-nymph.dts +++ b/arch/arm/boot/dts/imx6dl-pico-nymph.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-nymph", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-pi.dts b/arch/arm/boot/dts/imx6dl-pico-pi.dts index b7b1c07f96f3..4590e8ad9a91 100644 --- a/arch/arm/boot/dts/imx6dl-pico-pi.dts +++ b/arch/arm/boot/dts/imx6dl-pico-pi.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-pi", "fsl,imx6dl"; }; From 8fc8e8129e1aab1c7adfdb7c079eb0aa3d6f066b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:42 +0200 Subject: [PATCH 19/40] ARM: dts: imx6dl: add compatibles for Aristainetos boards The Aristainetos and Aristainetos2 boards have only SoC compatible. Cc: Heiko Schocher Signed-off-by: Krzysztof Kozlowski Reviewed-by: Heiko Schocher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-aristainetos2_4.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos2_7.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos_4.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos_7.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts index b16603f27dce..dfa6f64d43cc 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts @@ -46,7 +46,7 @@ / { model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos2-imx6dl-4", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts index abb2a1b9ce08..5e15212eaf3a 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts @@ -46,7 +46,7 @@ / { model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 5c7e85300695..cc861a43eb58 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -10,7 +10,7 @@ / { model = "aristainetos i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos-imx6dl-4", "fsl,imx6dl"; backlight { compatible = "pwm-backlight"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index 4d58cb4436d9..b6cb78870cd5 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -10,7 +10,7 @@ / { model = "aristainetos i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos-imx6dl-7", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; From ef8b31051a85773fd4d5c3afb78d5f172affb256 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:58 +0200 Subject: [PATCH 20/40] ARM: dts: imx6sl-warp: correct vendor in compatible to Revotics The WaRP board (Wearable Development Platform) was apparently made by Revolution Robotics, Inc (brand: Revotics), not by "Warp". Correct the vendor in compatible to reflect this. The compatibles were not documented in the bindings before. Link: https://revotics.com/warp Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-warp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts index 408da704c459..9d7c8884892a 100644 --- a/arch/arm/boot/dts/imx6sl-warp.dts +++ b/arch/arm/boot/dts/imx6sl-warp.dts @@ -51,8 +51,8 @@ #include "imx6sl.dtsi" / { - model = "WaRP Board"; - compatible = "warp,imx6sl-warp", "fsl,imx6sl"; + model = "Revotics WaRP Board"; + compatible = "revotics,imx6sl-warp", "fsl,imx6sl"; memory@80000000 { device_type = "memory"; From a486d18c0a14649bc86052431b9f3eb88bcb0e15 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:59 +0200 Subject: [PATCH 21/40] ARM: dts: imx7s-warp: correct vendor in compatible to Element14 The WaRP7 board (Wearable Development Platform) was apparently made by Element14, not by "Warp". Correct the vendor in compatible to reflect this. The compatibles were not documented in the bindings before. Link: https://www.element14.com/community/docs/DOC-79058 Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index d6b4888fa686..569bbd84e371 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -10,8 +10,8 @@ #include "imx7s.dtsi" / { - model = "Warp i.MX7 Board"; - compatible = "warp,imx7s-warp", "fsl,imx7s"; + model = "Element14 Warp i.MX7 Board"; + compatible = "element14,imx7s-warp", "fsl,imx7s"; memory@80000000 { device_type = "memory"; From 97f1dd5ba28f45f1fd41285dc713c7cf391f2cd7 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:47 +0200 Subject: [PATCH 22/40] ARM: dts: imx: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. DTC arch/arm/boot/dts/imx53-ppd.dt.yaml CHECK arch/arm/boot/dts/imx53-ppd.dt.yaml arch/arm/boot/dts/imx53-ppd.dt.yaml: leds-brightness: 'alarm-brightness' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml CHECK arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml: pwmleds: 'blue', 'green', 'red' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml Signed-off-by: Alexander Dahl Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 15 ++++++++------- arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 4 ++-- arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 8 ++++---- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index f7dcdf96e5c0..b480614efb30 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -176,36 +176,37 @@ power-supply = <®_3v3_lcd>; }; - leds-brightness { + led-controller-1 { compatible = "pwm-leds"; - alarm-brightness { + led-1 { + label = "alarm-brightness"; pwms = <&pwm1 0 100000>; max-brightness = <255>; }; }; - leds { + led-controller-2 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_alarmled_pins>; - alarm1 { + led-2 { label = "alarm:red"; gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; }; - alarm2 { + led-3 { label = "alarm:yellow"; gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; }; - alarm3 { + led-4 { label = "alarm:blue"; gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; }; - alarm4 { + led-5 { label = "alarm:silenced"; gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index 67042793b0ca..1e530d892b76 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -55,12 +55,12 @@ pinctrl-0 = <&pinctrl_cubox_i_ir>; }; - pwmleds { + led-controller { compatible = "pwm-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_pwm1>; - front { + led-1 { active-low; label = "imx6:red:front"; max-brightness = <248>; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index 5547916870c7..b9a1401e6c6d 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -40,22 +40,22 @@ regulator-max-microvolt = <3300000>; }; - pwmleds { + led-controller { compatible = "pwm-leds"; - red { + led-1 { label = "red"; max-brightness = <255>; pwms = <&pwm6 0 50000>; }; - green { + led-2 { label = "green"; max-brightness = <255>; pwms = <&pwm2 0 50000>; }; - blue { + led-3 { label = "blue"; max-brightness = <255>; pwms = <&pwm1 0 50000>; From 73db215119963918afe446c6cec76e2d421aa33c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 16 Oct 2020 09:51:58 +0200 Subject: [PATCH 23/40] ARM: dts: imx6/7: sync fsl,stop-mode with current flexcan driver After this patch we need 2 arguments less for the fsl,stop-mode property: | commit d9b081e3fc4bdc33e672dcb7bb256394909432fc | Author: Marc Kleine-Budde | Date: Sun Jun 14 21:09:20 2020 +0200 | | can: flexcan: remove ack_grp and ack_bit handling from driver | | Since commit: | | 048e3a34a2e7 can: flexcan: poll MCR_LPM_ACK instead of GPR ACK for stop mode acknowledgment | | the driver polls the IP core's internal bit MCR[LPM_ACK] as stop mode | acknowledge and not the acknowledgment on chip level. | | This means the 4th and 5th value of the property "fsl,stop-mode" isn't used | anymore. This patch removes the used "ack_gpr" and "ack_bit" from the driver. This patch removes the two last arguments, as they are not needed anymore. Signed-off-by: Oleksij Rempel Reviewed-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6sx.dtsi | 4 ++-- arch/arm/boot/dts/imx6ul.dtsi | 4 ++-- arch/arm/boot/dts/imx7s.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 7a8837cbe21b..bc98b63922b0 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -549,7 +549,7 @@ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, <&clks IMX6QDL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 28 0x10 17>; + fsl,stop-mode = <&gpr 0x34 28>; status = "disabled"; }; @@ -560,7 +560,7 @@ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, <&clks IMX6QDL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 29 0x10 18>; + fsl,stop-mode = <&gpr 0x34 29>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index dfdca1804f9f..6c604c38c790 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -463,7 +463,7 @@ clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -474,7 +474,7 @@ clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index d7d9f3e46b92..713a4bb341db 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -430,7 +430,7 @@ clocks = <&clks IMX6UL_CLK_CAN1_IPG>, <&clks IMX6UL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -441,7 +441,7 @@ clocks = <&clks IMX6UL_CLK_CAN2_IPG>, <&clks IMX6UL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 84d9cc13afb9..b58262acba11 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -971,7 +971,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN1_ROOT_CLK>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -982,7 +982,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN2_ROOT_CLK>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; From 5c8b3b8a182cbc1ccdfcdeea9b25dd2c12a8148f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 1 Nov 2020 19:29:53 +0800 Subject: [PATCH 24/40] ARM: dts: imx: add usb alias Add usb alias for bootloader searching the controller in correct order. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++++ arch/arm/boot/dts/imx6sl.dtsi | 3 +++ arch/arm/boot/dts/imx6sll.dtsi | 2 ++ arch/arm/boot/dts/imx6sx.dtsi | 3 +++ arch/arm/boot/dts/imx6ul.dtsi | 2 ++ arch/arm/boot/dts/imx7d.dtsi | 6 ++++++ arch/arm/boot/dts/imx7s.dtsi | 2 ++ 7 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index bc98b63922b0..cb2a8ef9070c 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -45,6 +45,10 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg; + usb1 = &usbh1; + usb2 = &usbh2; + usb3 = &usbh3; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 91a8c54d5e11..997b96c1c47b 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -39,6 +39,9 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 0b622201a1f3..04f8d637a501 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -36,6 +36,8 @@ spi1 = &ecspi2; spi3 = &ecspi3; spi4 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 6c604c38c790..8516730778df 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -49,6 +49,9 @@ spi2 = &ecspi3; spi3 = &ecspi4; spi4 = &ecspi5; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 713a4bb341db..ccbcbac80663 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -47,6 +47,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index cff875b80b60..b0bcfa9094a3 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -7,6 +7,12 @@ #include / { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + }; + cpus { cpu0: cpu@0 { clock-frequency = <996000000>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index b58262acba11..251007a7b836 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -47,6 +47,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbh; }; cpus { From 895387231e54e83bd0779afdea125df4d79c91a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 31 Oct 2020 22:07:29 +0100 Subject: [PATCH 25/40] ARM: dts: imx50-kobo-aura: Add 'grp' suffix to pinctrl node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i.MX pinctrl group nodes should have names that ends with 'grp'. Reported-by: Krzysztof Kozlowski Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-kobo-aura.dts | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts index a0eaf869b913..53b3995d37e7 100644 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -139,7 +139,7 @@ }; &iomuxc { - pinctrl_gpiokeys: gpiokeys { + pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = < MX50_PAD_CSPI_MISO__GPIO4_10 0x0 MX50_PAD_SD2_D7__GPIO5_15 0x0 @@ -147,34 +147,34 @@ >; }; - pinctrl_i2c1: i2c1 { + pinctrl_i2c1: i2c1grp { fsl,pins = < MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd >; }; - pinctrl_i2c2: i2c2 { + pinctrl_i2c2: i2c2grp { fsl,pins = < MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd >; }; - pinctrl_i2c3: i2c3 { + pinctrl_i2c3: i2c3grp { fsl,pins = < MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd >; }; - pinctrl_leds: leds { + pinctrl_leds: ledsgrp { fsl,pins = < MX50_PAD_PWM1__GPIO6_24 0x0 >; }; - pinctrl_sd1: sd1 { + pinctrl_sd1: sd1grp { fsl,pins = < MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 @@ -187,7 +187,7 @@ >; }; - pinctrl_sd2: sd2 { + pinctrl_sd2: sd2grp { fsl,pins = < MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 @@ -198,19 +198,19 @@ >; }; - pinctrl_sd2_reset: sd2-reset { + pinctrl_sd2_reset: sd2-resetgrp { fsl,pins = < MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 >; }; - pinctrl_sd2_vmmc: sd2-vmmc { + pinctrl_sd2_vmmc: sd2-vmmcgrp { fsl,pins = < MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 >; }; - pinctrl_sd3: sd3 { + pinctrl_sd3: sd3grp { fsl,pins = < MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 @@ -225,14 +225,14 @@ >; }; - pinctrl_uart2: uart2 { + pinctrl_uart2: uart2grp { fsl,pins = < MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 >; }; - pinctrl_usbphy: usbphy { + pinctrl_usbphy: usbphygrp { fsl,pins = < MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 >; From f4d0fea16ad771f1f3c930251af90f8b33d9fa66 Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 29 Oct 2020 08:03:22 +0100 Subject: [PATCH 26/40] ARM: dts: imx6ul: segin: Add phyBOARD-Segin with eMMC phyCORE-i.MX6UL Add a PHYTEC phyBOARD-Segin full featured with phyCORE-i.MX 6UL with eMMC and following features: - i.MX 6UL - 512 MB RAM - eMMC - USB Host/OTG - 2x 100 Mbit/s Ethernet - RS232 - CAN Signed-off-by: Yunus Bas Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../dts/imx6ul-phytec-segin-ff-rdk-emmc.dts | 93 +++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..654692919a27 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -622,6 +622,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-pico-pi.dtb \ + imx6ul-phytec-segin-ff-rdk-emmc.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts new file mode 100644 index 000000000000..4a25122e0da2 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-segin.dtsi" +#include "imx6ul-phytec-segin-peb-eval-01.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; + compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10", + "phytec,imx6ul-pcl063","fsl,imx6ul"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; From 6d4e1ff5281996efe6a2b9bc58cdcdd446bb52a4 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 29 Oct 2020 08:03:23 +0100 Subject: [PATCH 27/40] ARM: dts: imx6ul: phytec: Add support for optional PEB-AV-02 LCD adapter The PHYTEC PEB-AV-02 adapter adds the capability to connect a parallel LCD display to the phyBOARD-Segin full featured, either with capacitive or resistive touch. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- .../dts/imx6ul-phytec-segin-ff-rdk-emmc.dts | 1 + .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 + .../dts/imx6ul-phytec-segin-peb-av-02.dtsi | 150 ++++++++++++++++++ arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 43 ----- .../dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 1 + .../dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 + .../dts/imx6ull-phytec-segin-peb-av-02.dtsi | 26 +++ arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 7 - 8 files changed, 180 insertions(+), 50 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts index 4a25122e0da2..cfc744f8fcad 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" +#include "imx6ul-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts index 699dfcbf9a60..bff98e676980 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" +#include "imx6ul-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi new file mode 100644 index 000000000000..b511c6dec427 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2016, 2020 PHYTEC Messtechnik + * Author: Christian Hemp + * Author: Stefan Riedmueller + */ + +/ { + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + power-supply = <®_backlight_en>; + pwms = <&pwm3 0 5000000>; + status = "disabled"; + }; + + lcd_panel: lcd-panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&backlight_lcd>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_parallel_out>; + }; + }; + }; + + reg_backlight_en: regulator-backlight-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_en>; + regulator-name = "backlight-lcd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c1 { + edt_ft5406: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5406>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + status = "disabled"; + }; + + stmpe: touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + touchscreen-inverted-x = <1>; + touchscreen-inverted-y = <1>; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat>; + status = "disabled"; + + port { + lcdif_parallel_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_edt_ft5406: edtft5406grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_backlight_en: bachlightengrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x59 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x59 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x59 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x59 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x59 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x59 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x59 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x59 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x59 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x59 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x59 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x59 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x59 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x59 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x59 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x59 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x59 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x59 + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x59 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x59 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x59 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x59 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 7367279748f4..95e4080dd0a6 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -130,31 +130,6 @@ status = "disabled"; }; - stmpe: touchscreen@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - status = "disabled"; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; - }; - i2c_rtc: rtc@68 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc_int>; @@ -176,12 +151,6 @@ }; }; -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; @@ -267,12 +236,6 @@ >; }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 - >; - }; - pinctrl_rtc_int: rtcintgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 @@ -289,12 +252,6 @@ >; }; - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; - pinctrl_uart5: uart5grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts index 9648d4ecaf58..8e2a4c5d7765 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts index 656baf846453..c8d3eff9ed4b 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi new file mode 100644 index 000000000000..06bb7f327780 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-segin-peb-av-02.dtsi" + +&iomuxc { + /delete-node/ edtft5406grp; + /delete-node/ stmpegrp; +}; + +&iomuxc_snvs { + pinctrl_edt_ft5406: edtft5406grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi index c1595fc785f7..e287a0453b5f 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi @@ -14,7 +14,6 @@ &iomuxc { /delete-node/ flexcan1engrp; /delete-node/ rtcintgrp; - /delete-node/ stmpegrp; }; &iomuxc_snvs { @@ -29,10 +28,4 @@ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 >; }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; }; From 93c0289c11b08467c0c998d35f050e6664bbf99c Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 29 Oct 2020 08:03:24 +0100 Subject: [PATCH 28/40] ARM: dts: imx6ul: segin: peb-av-02: Mark stmpe touch as wakeup-source Mark the STMPE resistive touch controller as a wakeup-source. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index b511c6dec427..7cda6944501d 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -58,6 +58,7 @@ pinctrl-0 = <&pinctrl_stmpe>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio5>; + wakeup-source; status = "disabled"; stmpe_touchscreen { From df0852c234d9a73ad2469cd0562ba212a422c374 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 30 Oct 2020 15:00:29 +0100 Subject: [PATCH 29/40] ARM: dts: add Altesco I6P board Altesco (Altus-Escon-Company BV) I6P is a part of the diagnostic system for the vehicle inspection stations. Co-developed-by: David Jander Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-alti6p.dts | 564 ++++++++++++++++++++++++++++ 2 files changed, 565 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-alti6p.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 654692919a27..526e6c237a9c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -414,6 +414,7 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-usbarmory.dtb \ imx53-voipac-bsb.dtb dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-alti6p.dtb \ imx6dl-apf6dev.dtb \ imx6dl-aristainetos_4.dtb \ imx6dl-aristainetos_7.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts new file mode 100644 index 000000000000..4329b372d8cb --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-alti6p.dts @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Altesco I6P Board"; + compatible = "alt,alti6p", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + i2c2-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c2>; + mux-controls = <&i2c_mux>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c4-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c4>; + mux-controls = <&i2c_mux>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-debug1 { + function = LED_FUNCTION_SD; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + i2c_mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2cmux>; + + mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>, + <&gpio5 11 GPIO_ACTIVE_HIGH>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clock_ksz8081>; + clock-names = "ipg", "ahb", "ptp"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "USB_H1_OC", "", "", "", "", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "I2C_EN13", "I2C_EN24", "", "", "", "", + "", "", "", "", "", "AUDIO_RESET", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +/* DDC */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* external interface, device are configured from user space */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&i2c4 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T configure DDC + * pins for HDMI! + */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1 + MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2cmux: i2cmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x8 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1B058 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1B058 + + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; From d1f1858f51be4d7900fe2bac6394c8dfc641f2c4 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 2 Nov 2020 10:02:12 +0100 Subject: [PATCH 30/40] ARM: dts: add Van der Laan LANMCU board Van der Laan LANMCU is a module for the food storage rooms to control proper gas composition. Co-developed-by: Robin van der Gracht Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-lanmcu.dts | 470 ++++++++++++++++++++++++++++ 2 files changed, 471 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-lanmcu.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 526e6c237a9c..d3275fe3095f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -451,6 +451,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ + imx6dl-lanmcu.dtb \ imx6dl-mamoj.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/imx6dl-lanmcu.dts new file mode 100644 index 000000000000..6b6e6fcdea9c --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-lanmcu.dts @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2019 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Van der Laan LANMCU"; + compatible = "vdl,lanmcu", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 1000>; + num-interpolated-steps = <20>; + default-brightness-level = <19>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "edt,etm0700g0bdh6"; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clock_ksz8081>; + clock-names = "ipg", "ahb", "ptp"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "DEBUG_0", "BL_PWM", "", "", "", "", "", "", + "", "", "", "", "", "", "", "ENET_LED_GREEN", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "TS_INT", "USB_OTG1_OC", "USB_OTG1_PWR", "", + "", "", "", "", "UART2_CTS", "", "UART3_CTS", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "ENET_RST", "ENET_INT", + "", "", "I2C1_SDA", "I2C1_SCL", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "WLAN_REG_ON", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "EMMC_RST", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts_edt>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + + touchscreen-fuzz-x = <0>; + touchscreen-fuzz-y = <0>; + + /* Touch screen calibration */ + threshold = <50>; + gain = <5>; + offset = <10>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_ts_edt: ts1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_wifi_npd: wifigrp { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; From 1186a522c302e01f1737b28e353bac137c47aca8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 Nov 2020 19:50:34 +0100 Subject: [PATCH 31/40] ARM: dts: imx6q-pico: fix board compatibles There are four flavors of TechNexion PICO-IMX6 boards. They have their own DTSes, even though in Dwarf, Nymph and Pi are exactly the same. They also have their own bindings so adjust the compatibles to match the bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-pico-dwarf.dts | 2 +- arch/arm/boot/dts/imx6q-pico-hobbit.dts | 2 +- arch/arm/boot/dts/imx6q-pico-nymph.dts | 2 +- arch/arm/boot/dts/imx6q-pico-pi.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/imx6q-pico-dwarf.dts index 618d2743e1e9..479a63ed42af 100644 --- a/arch/arm/boot/dts/imx6q-pico-dwarf.dts +++ b/arch/arm/boot/dts/imx6q-pico-dwarf.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-dwarf", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/imx6q-pico-hobbit.dts index 7a666507b456..b767131068f5 100644 --- a/arch/arm/boot/dts/imx6q-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6q-pico-hobbit.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-hobbit", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-nymph.dts b/arch/arm/boot/dts/imx6q-pico-nymph.dts index fe5a7becc9e5..e8ad4c12b263 100644 --- a/arch/arm/boot/dts/imx6q-pico-nymph.dts +++ b/arch/arm/boot/dts/imx6q-pico-nymph.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-nymph", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-pi.dts b/arch/arm/boot/dts/imx6q-pico-pi.dts index 9413f0a68f54..cc2394ddad6c 100644 --- a/arch/arm/boot/dts/imx6q-pico-pi.dts +++ b/arch/arm/boot/dts/imx6q-pico-pi.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and PI baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-pi", "fsl,imx6q"; }; From 21658d51cf1ea88c04652a3852a190bb905cd91e Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 11 Nov 2020 14:05:05 +0100 Subject: [PATCH 32/40] ARM: dts: imx: Change flexcan node name to "can" Change i.MX SoCs nand node name from "flexcan" to "can" to be compliant with yaml schema, it requires the nodename to be "can". This fixes the following error found by dtbs_check: arch/arm/boot/dts/imx6dl-apf6dev.dt.yaml: flexcan@2090000: $nodename:0: 'flexcan@2090000' does not match '^can(@.*)?$' From schema: Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml Cc: Shawn Guo Cc: devicetree@vger.kernel.org Signed-off-by: Marc Kleine-Budde Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6ul.dtsi | 4 ++-- arch/arm/boot/dts/vfxxx.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index cb2a8ef9070c..6f59a99cbe82 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -546,7 +546,7 @@ status = "disabled"; }; - can1: flexcan@2090000 { + can1: can@2090000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; @@ -557,7 +557,7 @@ status = "disabled"; }; - can2: flexcan@2094000 { + can2: can@2094000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index ccbcbac80663..9d3411cc597b 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -425,7 +425,7 @@ status = "disabled"; }; - can1: flexcan@2090000 { + can1: can@2090000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = ; @@ -436,7 +436,7 @@ status = "disabled"; }; - can2: flexcan@2094000 { + can2: can@2094000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = ; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 0c8d15fd9253..d53f9c9db8bf 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -95,7 +95,7 @@ status = "disabled"; }; - can0: flexcan@40020000 { + can0: can@40020000 { compatible = "fsl,vf610-flexcan"; reg = <0x40020000 0x4000>; interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; @@ -681,7 +681,7 @@ status = "disabled"; }; - can1: flexcan@400d4000 { + can1: can@400d4000 { compatible = "fsl,vf610-flexcan"; reg = <0x400d4000 0x4000>; interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; From b9639a8b5ef1fa90fc0152db15588a9fe601c4b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 13 Nov 2020 00:30:54 +0100 Subject: [PATCH 33/40] ARM: dts: imx50-kobo-aura: Enable eKTF2132 touchscreen MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Kobo Aura has an eKTF2132 touchscreen controller. Although the vendor kernel toggles a reset pin (GPIO5-12) during the startup sequence, the touchscreen works without it. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-kobo-aura.dts | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts index 53b3995d37e7..97cfd970fe74 100644 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx50.dtsi" #include +#include / { model = "Kobo Aura (N514)"; @@ -119,7 +120,14 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - /* TODO: ektf2132 touch controller at 0x15 */ + touchscreen@15 { + reg = <0x15>; + compatible = "elan,ektf2132"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + power-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + interrupts-extended = <&gpio5 13 IRQ_TYPE_EDGE_FALLING>; + }; }; &i2c2 { @@ -225,6 +233,13 @@ >; }; + pinctrl_ts: tsgrp { + fsl,pins = < + MX50_PAD_CSPI_MOSI__GPIO4_9 0x0 + MX50_PAD_SD2_D5__GPIO5_13 0x0 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 From 7a1980567fa0b8f37c0fc7d9ca0c7c70724bae3d Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 2 Nov 2020 15:26:51 +0800 Subject: [PATCH 34/40] ARM: dts: ls1021a: fix flextimer failed to wake system The data of property 'fsl,rcpm-wakeup' is not corrcet, which causing RCPM driver incorrectly program register IPPDEXPCR1, then flextimer is wrongly clock gated during system suspend, can't send interrupt to wake. Signed-off-by: Ran Wang Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 827373ef1a54..e12809d646a2 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -1013,7 +1013,7 @@ compatible = "fsl,ls1021a-ftm-alarm"; reg = <0x0 0x29d0000 0x0 0x10000>; reg-names = "ftm"; - fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; interrupts = ; big-endian; }; From 4ebd35bfb1831e549467a0deda99b39acb62cf50 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 2 Nov 2020 15:26:52 +0800 Subject: [PATCH 35/40] ARM: dts: ls1021a: fix rcpm failed to claim resource The range of dcfg reg is wrong, which overlap with other device, such as rcpm. This issue causing rcpm driver failed to claim reg resource when calling devm_ioremap_resource(). Signed-off-by: Ran Wang Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index e12809d646a2..16744f64e431 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -173,7 +173,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; From b675aaee5464ca8384853145578e662e54debf7a Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Tue, 17 Nov 2020 11:43:05 +0800 Subject: [PATCH 36/40] ARM: dts: ls1021a: update calibration table for TMU module Update the calibration table to make the temperature more accurate. Signed-off-by: Yuantian Tang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 71 ++++++++++++++++------------------ 1 file changed, 34 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 16744f64e431..007dd2bd0595 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -288,46 +288,43 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = ; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; - fsl,tmu-calibration = <0x00000000 0x0000000f - 0x00000001 0x00000017 - 0x00000002 0x0000001e - 0x00000003 0x00000026 - 0x00000004 0x0000002e - 0x00000005 0x00000035 - 0x00000006 0x0000003d - 0x00000007 0x00000044 - 0x00000008 0x0000004c - 0x00000009 0x00000053 - 0x0000000a 0x0000005b - 0x0000000b 0x00000064 + fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; + fsl,tmu-calibration = <0x00000000 0x00000020 + 0x00000001 0x00000024 + 0x00000002 0x0000002a + 0x00000003 0x00000032 + 0x00000004 0x00000038 + 0x00000005 0x0000003e + 0x00000006 0x00000043 + 0x00000007 0x0000004a + 0x00000008 0x00000050 + 0x00000009 0x00000059 + 0x0000000a 0x0000005f + 0x0000000b 0x00000066 - 0x00010000 0x00000011 - 0x00010001 0x0000001c - 0x00010002 0x00000024 - 0x00010003 0x0000002b - 0x00010004 0x00000034 - 0x00010005 0x00000039 - 0x00010006 0x00000042 - 0x00010007 0x0000004c - 0x00010008 0x00000051 - 0x00010009 0x0000005a - 0x0001000a 0x00000063 + 0x00010000 0x00000023 + 0x00010001 0x0000002b + 0x00010002 0x00000033 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000054 + 0x00010007 0x0000005c + 0x00010008 0x00000065 + 0x00010009 0x0000006f - 0x00020000 0x00000013 - 0x00020001 0x00000019 - 0x00020002 0x00000024 - 0x00020003 0x0000002c - 0x00020004 0x00000035 - 0x00020005 0x0000003d - 0x00020006 0x00000046 - 0x00020007 0x00000050 - 0x00020008 0x00000059 + 0x00020000 0x00000029 + 0x00020001 0x00000033 + 0x00020002 0x0000003d + 0x00020003 0x00000048 + 0x00020004 0x00000054 + 0x00020005 0x00000060 + 0x00020006 0x0000006c - 0x00030000 0x00000002 - 0x00030001 0x0000000d - 0x00030002 0x00000019 - 0x00030003 0x00000024>; + 0x00030000 0x00000025 + 0x00030001 0x00000033 + 0x00030002 0x00000043 + 0x00030003 0x00000055>; #thermal-sensor-cells = <1>; }; From 1e1a5afde9f79386815233aacf48e188a6710fc2 Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 18 Nov 2020 11:21:19 +0100 Subject: [PATCH 37/40] ARM: dts: imx7: add support for kamstrup flex concentrator This adds support for the OMNIA Flex Concentrator product from Kamstrup A/S. It's providing radio mesh communication infrastructure for smart electricity meters. Kamstrup OMNIA is a modular and scalable smart grid platform. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/imx7d-flex-concentrator-mfg.dts | 25 ++ arch/arm/boot/dts/imx7d-flex-concentrator.dts | 314 ++++++++++++++++++ 3 files changed, 341 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts create mode 100644 arch/arm/boot/dts/imx7d-flex-concentrator.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d3275fe3095f..0a7544e01f02 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -644,6 +644,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-colibri-emmc-aster.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ + imx7d-flex-concentrator.dtb \ + imx7d-flex-concentrator-mfg.dtb \ imx7d-mba7.dtb \ imx7d-meerkat96.dtb \ imx7d-nitrogen7.dtb \ diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts b/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts new file mode 100644 index 000000000000..a6d68165fb1e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Kamstrup OMNIA Flex Concentrator in + * manufacturing/debugging mode. + * + * Copyright (C) 2020 Kamstrup A/S + * Author: Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-flex-concentrator.dts" + +/ { + model = "Kamstrup OMNIA Flex Concentrator - Manufacturing"; + compatible = "kam,imx7d-flex-concentrator-mfg", "fsl,imx7d"; + + chosen { + stdout-path = &uart4; + }; +}; + +&uart4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/imx7d-flex-concentrator.dts new file mode 100644 index 000000000000..84b095279e65 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-flex-concentrator.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Kamstrup OMNIA Flex Concentrator. + * + * Copyright (C) 2020 Kamstrup A/S + * Author: Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-tqma7.dtsi" + +/* One I2C device on TQMa7 SoM is not mounted */ +/delete-node/ &ds1339; + +/ { + model = "Kamstrup OMNIA Flex Concentrator"; + compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d"; + + memory@80000000 { + device_type = "memory"; + /* 1024 MB - TQMa7D board configuration */ + reg = <0x80000000 0x40000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_REF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&sw2_reg>; + }; + + /* + * Human Machine Interface consists of 4 dual red/green LEDs. + * hmi-a:green is controlled directly by the switch-mode power supply. + * hmi-a:red is not used. + */ + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "hmi-b:red:heartbeat-degraded"; + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "hmi-b:green:heartbeat-running"; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "hmi-c:red:mesh-error"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "hmi-c:green:mesh-activity"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "hmi-d:red:omnia-error"; + gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + label = "hmi-d:green:omnia-activity"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * Errata e10574 board restart workaround. + */ + gpio-restart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restart>; + compatible = "gpio-restart"; + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* + * Analog signals + * ADC1_IN0: SMPS - 5V output monitor (voltage divider: 1/0.2806) + */ +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-chipselects = <1>; + cs-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + status = "okay"; + + pcf2127: rtc@0 { + compatible = "nxp,pcf2127"; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + num-chipselects = <1>; + cs-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* + * ST chip maximum SPI clock frequency is 33 MHz. + * + * TCG specification - Section 6.4.1 Clocking: + * TPM shall support a SPI clock frequency range of 10-24 MHz. + */ + st33htph: tpm-tis@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + /* + * MDIO bus reset is used to generate PHY device reset before + * Ethernet PHY type ID auto-detection. Otherwise this communication + * fails as device does not answer when recommended reset circuit + * is used. + */ + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-delay-us = <100000>; + reset-post-delay-us = <500000>; + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + + /* Microchip/Micrel KSZ8081RNB */ + ethphy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + }; + }; +}; + +/* + * Detection signals for internal USB modules. + * Used for robust USB plug and play handling such as USB downstream port + * power-cycle and USB hub reset in case of misbehaving or crashed modules. + * + * SMPS - AC input monitor based on zero crossing. + * Used for last gasp notification. + */ +&gpio3 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "smps-ac-monitor", "", "usb-hub-reset", "", + "", "", "", "", "", "", "", "", + "", "module-b-detection", "", "module-a-detection", "", "", "", ""; +}; + +/* + * Tamper IRQ trigger timestamp reading. + * Used for sealed cover opened/closed notification. + */ +&gpio5 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "rtc-tamper-irq", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_misc>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c /* X2-15 */ + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 /* X2-18 */ + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 /* X2-13 */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x74 /* X2-20 */ + /* RTC - Tamper IRQ */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x3c /* X1-92 */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x7c /* X2-72 */ + MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x74 /* X2-68 */ + MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x74 /* X2-76 */ + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x74 /* X2-78 */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x03 /* X2-48 */ + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x03 /* X2-46 */ + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 /* X2-53 */ + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 /* X2-55 */ + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 /* X2-61 */ + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 /* X2-56 */ + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 /* X2-58 */ + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 /* X2-64 */ + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 /* X2-52 */ + /* PHY reset: SRE_FAST, DSE_X1 */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x00 /* X1-96 */ + /* Clock from PHY to MAC: 100kPU */ + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x70 /* X3-4 */ + /* PHY interrupt: 100kPU, HYS */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x78 /* X1-80 */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x14 /* X2-82 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* X1-82 */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* X1-84 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* X1-86 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* X1-88 */ + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x14 /* X1-90 */ + >; + }; + + pinctrl_misc: miscgrp { + fsl,pins = < + /* Module A detection (low = present) */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x7c /* X2-105 */ + /* Module B detection (low = present) */ + MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x7c /* X2-103 */ + /* SMPS - AC input monitor (high = failure) */ + MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x7c /* X2-88 */ + /* USB - Hub reset */ + MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x74 /* X2-92 */ + >; + }; + + pinctrl_restart: restartgrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x74 /* X1-94 */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e /* X3-14 */ + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 /* X3-16 */ + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c /* X3-11 */ + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 /* X3-9 */ + >; + }; + +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + dr_mode = "host"; + status = "okay"; +}; + +/* + * External watchdog feature provided by pcf2127. + */ +&wdog1 { + status = "disabled"; +}; From 708ed2649ad86dad2284acac6e4e6829a3cfd604 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Thu, 26 Nov 2020 20:22:52 +0100 Subject: [PATCH 38/40] ARM: dts: imx6qdl-kontron-samx6i: increase i2c-frequency Set it to max. allowed 375kHz for faster transfers. The limit is given by the erratum [1]. [1] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi index 265f5f3dbff6..b6a0b8809e74 100644 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -390,21 +390,21 @@ /* I2C_GP */ &i2c1 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; }; /* HDMI_CTRL */ &i2c2 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; }; /* I2C_PM */ &i2c3 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; From 35771b33dd987783171058e7db901f98ddd4c097 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 17 Nov 2020 14:13:54 +0100 Subject: [PATCH 39/40] ARM: dts: add Protonic WD3 board Protonic WD3 is a proof of concept platform for tractor e-cockpit applications Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6qp-prtwd3.dts | 553 ++++++++++++++++++++++++++++ 2 files changed, 554 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qp-prtwd3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0a7544e01f02..3ab9d58428cf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -583,6 +583,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-nitrogen6_max.dtb \ imx6qp-nitrogen6_som2.dtb \ imx6qp-phytec-mira-rdk-nand.dtb \ + imx6qp-prtwd3.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb \ imx6qp-tx6qp-8037.dtb \ diff --git a/arch/arm/boot/dts/imx6qp-prtwd3.dts b/arch/arm/boot/dts/imx6qp-prtwd3.dts new file mode 100644 index 000000000000..c42723989bc0 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-prtwd3.dts @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2018 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include "imx6qp.dtsi" + +/ { + model = "Protonic WD3 board"; + compatible = "prt,prtwd3", "fsl,imx6qp"; + + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_mcp251xfd: clock-mcp251xfd { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>; + + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH>; + + /* Microchip KSZ8081 */ + usbeth_phy: ethernet-phy@3 { + reg = <0x3>; + + interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <1000>; + clocks = <&clock_ksz8081>; + clock-names = "rmii-ref"; + micrel,led-mode = <0>; + }; + + tja1102_phy0: ethernet-phy@4 { + reg = <0x4>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <2000>; + #address-cells = <1>; + #size-cells = <0>; + + tja1102_phy1: ethernet-phy@5 { + reg = <0x5>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "usb"; + phy-handle = <&usbeth_phy>; + phy-mode = "rmii"; + }; + + port@1 { + reg = <1>; + label = "t1slave"; + phy-handle = <&tja1102_phy1>; + phy-mode = "rmii"; + }; + + port@2 { + reg = <2>; + label = "t1master"; + phy-handle = <&tja1102_phy0>; + phy-mode = "rmii"; + + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp251xfd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + reg = <0>; + clocks = <&clock_mcp251xfd>; + spi-max-frequency = <10000000>; + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + phy-mode = "rgmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031 */ + rgmii_phy: ethernet-phy@2 { + reg = <2>; + + interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "PHY3_RESET", "", "", "PHY3_INT", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3", + "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "", "", "", "", "", "", "", "", + "", "", "ECSPI2_SS0", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", + "", "", "", "", "", "", "", "", + "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "SW_RESET", "", "", + "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET", + "PHY0_INT", "", "", "", + "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD", + "", "", + "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ", + "DISP0_EN", "CAM_GPIO0"; +}; + +&gpio6 { + gpio-line-names = + "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD", + "CAM_LOCK", "", "POWER_TG", + "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "", + "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1", + "USB_ETH_CHG_ID2", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* VIN */ + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* VBUS */ + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* ICHG */ + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + /* CAN2_nINT */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Configure clock provider for RGMII ref clock */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + /* Configure clock consumer for RGMII ref clock */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + + /* SJA1105Q switch reset */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 + + /* phy3/rgmii_phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 + /* phy3/rgmii_phy int */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + /* phy0/usbeth_phy reset */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 + /* phy0/usbeth_phy int */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + + /* phy12/tja1102_phy0 reset */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 + /* phy12/tja1102_phy0 int */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 + /* phy12/tja1102_phy0 enable. Set 100K pull-up */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; From 327106e4217b8ef4f74640d7de15a0a287690aba Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 25 Nov 2020 17:18:13 +0100 Subject: [PATCH 40/40] ARM: dts: imx28: Fix label name for L2 switch The 'eth_switch' name has been misspelled in the imx28.dtsi file, so this change fixes it. Signed-off-by: Lukasz Majewski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 94dfbf5b3f34..bbe52150b165 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -1317,7 +1317,7 @@ status = "disabled"; }; - etn_switch: switch@800f8000 { + eth_switch: switch@800f8000 { reg = <0x800f8000 0x8000>; status = "disabled"; };