powerpc/fsl_booke: Avoid creating duplicate tlb1 entry
In the current implementation, the call to loadcam_multi() is wrapped
between switch_to_as1() and restore_to_as0() calls so, when it tries
to create its own temporary AS=1 TLB1 entry, it ends up duplicating
the existing one created by switch_to_as1(). Add a check to skip
creating the temporary entry if already running in AS=1.
Fixes: d9e1831a42
("powerpc/85xx: Load all early TLB entries at once")
Cc: stable@vger.kernel.org # v4.4+
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Acked-by: Scott Wood <oss@buserror.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200123111914.2565-1-laurentiu.tudor@nxp.com
This commit is contained in:
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@ -397,7 +397,7 @@ _GLOBAL(set_context)
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* extern void loadcam_entry(unsigned int index)
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* extern void loadcam_entry(unsigned int index)
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*
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*
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* Load TLBCAM[index] entry in to the L2 CAM MMU
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* Load TLBCAM[index] entry in to the L2 CAM MMU
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* Must preserve r7, r8, r9, and r10
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* Must preserve r7, r8, r9, r10 and r11
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*/
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*/
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_GLOBAL(loadcam_entry)
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_GLOBAL(loadcam_entry)
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mflr r5
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mflr r5
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@ -433,6 +433,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
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*/
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*/
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_GLOBAL(loadcam_multi)
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_GLOBAL(loadcam_multi)
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mflr r8
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mflr r8
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/* Don't switch to AS=1 if already there */
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mfmsr r11
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andi. r11,r11,MSR_IS
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bne 10f
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/*
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/*
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* Set up temporary TLB entry that is the same as what we're
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* Set up temporary TLB entry that is the same as what we're
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@ -458,6 +462,7 @@ _GLOBAL(loadcam_multi)
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mtmsr r6
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mtmsr r6
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isync
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isync
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10:
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mr r9,r3
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mr r9,r3
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add r10,r3,r4
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add r10,r3,r4
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2: bl loadcam_entry
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2: bl loadcam_entry
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@ -466,6 +471,10 @@ _GLOBAL(loadcam_multi)
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mr r3,r9
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mr r3,r9
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blt 2b
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blt 2b
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/* Don't return to AS=0 if we were in AS=1 at function start */
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andi. r11,r11,MSR_IS
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bne 3f
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/* Return to AS=0 and clear the temporary entry */
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/* Return to AS=0 and clear the temporary entry */
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mfmsr r6
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mfmsr r6
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rlwinm. r6,r6,0,~(MSR_IS|MSR_DS)
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rlwinm. r6,r6,0,~(MSR_IS|MSR_DS)
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@ -481,6 +490,7 @@ _GLOBAL(loadcam_multi)
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tlbwe
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tlbwe
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isync
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isync
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3:
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mtlr r8
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mtlr r8
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blr
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blr
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#endif
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#endif
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