forked from Minki/linux
i2c: iproc: use wrapper for read/write access
Use the following wrapper for read/write access of iProc i2c registers:
u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
u32 offset)
void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, u32 offset,
u32 val)
This preps the driver for support of indirect register access required
by certain SoCs with this iProc I2C block integrated
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Rayagonda Kokatanur
Wolfram Sang
parent
3f98ad45e5
commit
a9f0a81ef8
@ -212,6 +212,18 @@ static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
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static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
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bool enable);
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static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
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u32 offset)
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{
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return readl(iproc_i2c->base + offset);
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}
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static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
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u32 offset, u32 val)
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{
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writel(val, iproc_i2c->base + offset);
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}
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static void bcm_iproc_i2c_slave_init(
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struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
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{
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@ -219,37 +231,37 @@ static void bcm_iproc_i2c_slave_init(
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if (need_reset) {
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/* put controller in reset */
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val = readl(iproc_i2c->base + CFG_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
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val |= BIT(CFG_RESET_SHIFT);
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writel(val, iproc_i2c->base + CFG_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
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/* wait 100 usec per spec */
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udelay(100);
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/* bring controller out of reset */
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val &= ~(BIT(CFG_RESET_SHIFT));
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writel(val, iproc_i2c->base + CFG_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
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}
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/* flush TX/RX FIFOs */
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val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
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writel(val, iproc_i2c->base + S_FIFO_CTRL_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
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/* Maximum slave stretch time */
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val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
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val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
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val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
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writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
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/* Configure the slave address */
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val = readl(iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
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val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
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val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
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val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
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writel(val, iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
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/* clear all pending slave interrupts */
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writel(ISR_MASK_SLAVE, iproc_i2c->base + IS_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
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/* Enable interrupt register for any READ event */
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val = BIT(IE_S_RD_EVENT_SHIFT);
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@ -257,7 +269,7 @@ static void bcm_iproc_i2c_slave_init(
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val |= BIT(IE_S_RX_EVENT_SHIFT);
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/* Enable interrupt register for the Slave BUSY command */
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val |= BIT(IE_S_START_BUSY_SHIFT);
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writel(val, iproc_i2c->base + IE_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
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iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
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}
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@ -267,7 +279,7 @@ static void bcm_iproc_i2c_check_slave_status(
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{
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u32 val;
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val = readl(iproc_i2c->base + S_CMD_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
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val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
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if (val == S_CMD_STATUS_TIMEOUT) {
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@ -290,7 +302,7 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
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/* Start of transaction. check address and populate the direction */
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if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) {
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tmp = readl(iproc_i2c->base + S_RX_OFFSET);
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tmp = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
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rd_status = (tmp >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
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/* This condition checks whether the request is a new request */
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if (((rd_status == I2C_SLAVE_RX_START) &&
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@ -316,16 +328,16 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
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(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) {
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i2c_slave_event(iproc_i2c->slave,
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I2C_SLAVE_READ_PROCESSED, &value);
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writel(value, iproc_i2c->base + S_TX_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
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val = BIT(S_CMD_START_BUSY_SHIFT);
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writel(val, iproc_i2c->base + S_CMD_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
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}
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/* write request from master */
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if ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&
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(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) {
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val = readl(iproc_i2c->base + S_RX_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
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/* Its a write request by Master to Slave.
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* We read data present in receive FIFO
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*/
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@ -348,7 +360,7 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
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}
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/* clear interrupt status */
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writel(status, iproc_i2c->base + IS_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
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bcm_iproc_i2c_check_slave_status(iproc_i2c);
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return true;
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@ -360,12 +372,12 @@ static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
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/* Read valid data from RX FIFO */
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while (iproc_i2c->rx_bytes < msg->len) {
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if (!((readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET) >> M_FIFO_RX_CNT_SHIFT)
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if (!((iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET) >> M_FIFO_RX_CNT_SHIFT)
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& M_FIFO_RX_CNT_MASK))
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break;
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msg->buf[iproc_i2c->rx_bytes] =
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(readl(iproc_i2c->base + M_RX_OFFSET) >>
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(iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET) >>
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M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
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iproc_i2c->rx_bytes++;
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}
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@ -397,14 +409,15 @@ static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
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* Since this is the last byte, we should now
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* disable TX FIFO underrun interrupt
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*/
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tmp = readl(iproc_i2c->base + IE_OFFSET);
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tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
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tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
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writel(tmp, iproc_i2c->base + IE_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
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tmp);
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}
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}
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/* load data into TX FIFO */
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writel(val, iproc_i2c->base + M_TX_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
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}
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/* update number of transferred bytes */
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@ -421,16 +434,16 @@ static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
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if (bytes_left == 0) {
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if (iproc_i2c->irq) {
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/* finished reading all data, disable rx thld event */
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val = readl(iproc_i2c->base + IE_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
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val &= ~BIT(IS_M_RX_THLD_SHIFT);
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writel(val, iproc_i2c->base + IE_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
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}
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} else if (bytes_left < iproc_i2c->thld_bytes) {
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/* set bytes left as threshold */
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val = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
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val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
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val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
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iproc_i2c->thld_bytes = bytes_left;
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}
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/*
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@ -462,7 +475,7 @@ static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
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static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
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{
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struct bcm_iproc_i2c_dev *iproc_i2c = data;
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u32 status = readl(iproc_i2c->base + IS_OFFSET);
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u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
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bool ret;
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u32 sl_status = status & ISR_MASK_SLAVE;
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@ -480,7 +493,7 @@ static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
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/* process all master based events */
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bcm_iproc_i2c_process_m_event(iproc_i2c, status);
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writel(status, iproc_i2c->base + IS_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
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return IRQ_HANDLED;
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}
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@ -490,29 +503,29 @@ static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
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u32 val;
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/* put controller in reset */
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val = readl(iproc_i2c->base + CFG_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
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val |= BIT(CFG_RESET_SHIFT);
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val &= ~(BIT(CFG_EN_SHIFT));
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writel(val, iproc_i2c->base + CFG_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
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/* wait 100 usec per spec */
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udelay(100);
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/* bring controller out of reset */
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val &= ~(BIT(CFG_RESET_SHIFT));
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writel(val, iproc_i2c->base + CFG_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
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/* flush TX/RX FIFOs and set RX FIFO threshold to zero */
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val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
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/* disable all interrupts */
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val = readl(iproc_i2c->base + IE_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
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val &= ~(IE_M_ALL_INTERRUPT_MASK <<
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IE_M_ALL_INTERRUPT_SHIFT);
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writel(val, iproc_i2c->base + IE_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
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/* clear all pending interrupts */
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writel(0xffffffff, iproc_i2c->base + IS_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
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return 0;
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}
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@ -522,12 +535,12 @@ static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
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{
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u32 val;
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val = readl(iproc_i2c->base + CFG_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
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if (enable)
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val |= BIT(CFG_EN_SHIFT);
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else
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val &= ~BIT(CFG_EN_SHIFT);
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writel(val, iproc_i2c->base + CFG_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
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}
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static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
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@ -535,7 +548,7 @@ static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
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{
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u32 val;
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val = readl(iproc_i2c->base + M_CMD_OFFSET);
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val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
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val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
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switch (val) {
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@ -586,15 +599,15 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
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u32 val, status;
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int ret;
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writel(cmd, iproc_i2c->base + M_CMD_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
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if (iproc_i2c->irq) {
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time_left = wait_for_completion_timeout(&iproc_i2c->done,
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time_left);
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/* disable all interrupts */
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writel(0, iproc_i2c->base + IE_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
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/* read it back to flush the write */
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readl(iproc_i2c->base + IE_OFFSET);
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iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
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/* make sure the interrupt handler isn't running */
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synchronize_irq(iproc_i2c->irq);
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@ -602,9 +615,10 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
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unsigned long timeout = jiffies + time_left;
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do {
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status = readl(iproc_i2c->base + IS_OFFSET) & ISR_MASK;
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status = iproc_i2c_rd_reg(iproc_i2c,
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IS_OFFSET) & ISR_MASK;
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bcm_iproc_i2c_process_m_event(iproc_i2c, status);
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writel(status, iproc_i2c->base + IS_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
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if (time_after(jiffies, timeout)) {
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time_left = 0;
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@ -621,7 +635,7 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
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/* flush both TX/RX FIFOs */
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val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
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return -ETIMEDOUT;
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}
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@ -629,7 +643,7 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
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if (ret) {
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/* flush both TX/RX FIFOs */
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val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
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return ret;
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}
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@ -645,8 +659,8 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
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unsigned int tx_bytes;
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/* check if bus is busy */
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if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
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BIT(M_CMD_START_BUSY_SHIFT))) {
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if (!!(iproc_i2c_rd_reg(iproc_i2c,
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M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
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dev_warn(iproc_i2c->device, "bus is busy\n");
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return -EBUSY;
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}
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@ -655,7 +669,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
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/* format and load slave address into the TX FIFO */
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addr = i2c_8bit_addr_from_msg(msg);
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writel(addr, iproc_i2c->base + M_TX_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
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/*
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* For a write transaction, load data into the TX FIFO. Only allow
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@ -671,7 +685,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
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if (i == msg->len - 1)
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val |= 1 << M_TX_WR_STATUS_SHIFT;
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writel(val, iproc_i2c->base + M_TX_OFFSET);
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iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
|
||||
}
|
||||
iproc_i2c->tx_bytes = tx_bytes;
|
||||
}
|
||||
@ -711,10 +725,10 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
|
||||
iproc_i2c->thld_bytes = msg->len;
|
||||
|
||||
/* set threshold value */
|
||||
tmp = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET);
|
||||
tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
|
||||
tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
|
||||
tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
|
||||
writel(tmp, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
|
||||
iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
|
||||
|
||||
/* enable the RX threshold interrupt */
|
||||
val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
|
||||
@ -726,7 +740,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
|
||||
}
|
||||
|
||||
if (iproc_i2c->irq)
|
||||
writel(val_intr_en, iproc_i2c->base + IE_OFFSET);
|
||||
iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
|
||||
|
||||
return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
|
||||
}
|
||||
@ -790,10 +804,10 @@ static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
|
||||
}
|
||||
|
||||
iproc_i2c->bus_speed = bus_speed;
|
||||
val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
|
||||
val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
|
||||
val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
|
||||
val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
|
||||
writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
|
||||
iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
|
||||
|
||||
dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
|
||||
|
||||
@ -868,8 +882,8 @@ static int bcm_iproc_i2c_remove(struct platform_device *pdev)
|
||||
* Make sure there's no pending interrupt when we remove the
|
||||
* adapter
|
||||
*/
|
||||
writel(0, iproc_i2c->base + IE_OFFSET);
|
||||
readl(iproc_i2c->base + IE_OFFSET);
|
||||
iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
|
||||
iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
|
||||
synchronize_irq(iproc_i2c->irq);
|
||||
}
|
||||
|
||||
@ -890,8 +904,8 @@ static int bcm_iproc_i2c_suspend(struct device *dev)
|
||||
* Make sure there's no pending interrupt when we go into
|
||||
* suspend
|
||||
*/
|
||||
writel(0, iproc_i2c->base + IE_OFFSET);
|
||||
readl(iproc_i2c->base + IE_OFFSET);
|
||||
iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
|
||||
iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
|
||||
synchronize_irq(iproc_i2c->irq);
|
||||
}
|
||||
|
||||
@ -916,10 +930,10 @@ static int bcm_iproc_i2c_resume(struct device *dev)
|
||||
return ret;
|
||||
|
||||
/* configure to the desired bus speed */
|
||||
val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
|
||||
val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
|
||||
val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
|
||||
val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
|
||||
writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
|
||||
iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
|
||||
|
||||
bcm_iproc_i2c_enable_disable(iproc_i2c, true);
|
||||
|
||||
@ -963,15 +977,15 @@ static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
|
||||
iproc_i2c->slave = NULL;
|
||||
|
||||
/* disable all slave interrupts */
|
||||
tmp = readl(iproc_i2c->base + IE_OFFSET);
|
||||
tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
|
||||
tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
|
||||
IE_S_ALL_INTERRUPT_SHIFT);
|
||||
writel(tmp, iproc_i2c->base + IE_OFFSET);
|
||||
iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
|
||||
|
||||
/* Erase the slave address programmed */
|
||||
tmp = readl(iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET);
|
||||
tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
|
||||
tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
|
||||
writel(tmp, iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET);
|
||||
iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user