forked from Minki/linux
net: ethernet: ti: am65-cpsw: prepare xmit/rx path for multi-port devices in mac-only mode
This patch adds multi-port support to TI AM65x CPSW driver xmit/rx path in preparation for adding support for multi-port devices, like Main CPSW0 on K3 J721E SoC or future CPSW3g on K3 AM64x SoC. Hence DMA channels are common/shared for all ext Ports and the RX/TX NAPI and DMA processing going to be assigned to first available netdev this patch: - ensures all RX descriptors fields are initialized; - adds synchronization for TX DMA push/pop operation (locking) as Networking core locks are not enough any more; - updates TX bql processing for every packet in am65_cpsw_nuss_tx_compl_packets() as every completed TX skb can have different ndev assigned (come from different netdevs). To avoid performance issues for existing one-port CPSW2g devices the above changes are done only for multi-port devices by splitting xmit path for one-port and multi-port devices. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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97067aaf12
commit
a9e60cf0b4
@ -375,7 +375,7 @@ static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common,
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cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT,
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AM65_CPSW_NAV_PS_DATA_SIZE);
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cppi5_hdesc_attach_buf(desc_rx, 0, 0, buf_dma, skb_tailroom(skb));
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cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb));
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swdata = cppi5_hdesc_get_swdata(desc_rx);
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*((void **)swdata) = skb;
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@ -911,10 +911,57 @@ static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma)
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dev_kfree_skb_any(skb);
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}
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static struct sk_buff *
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am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn,
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dma_addr_t desc_dma)
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{
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struct am65_cpsw_ndev_priv *ndev_priv;
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struct am65_cpsw_ndev_stats *stats;
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struct cppi5_host_desc_t *desc_tx;
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struct net_device *ndev;
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struct sk_buff *skb;
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void **swdata;
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desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
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desc_dma);
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swdata = cppi5_hdesc_get_swdata(desc_tx);
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skb = *(swdata);
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am65_cpsw_nuss_xmit_free(tx_chn, tx_chn->common->dev, desc_tx);
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ndev = skb->dev;
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am65_cpts_tx_timestamp(tx_chn->common->cpts, skb);
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ndev_priv = netdev_priv(ndev);
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stats = this_cpu_ptr(ndev_priv->stats);
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u64_stats_update_begin(&stats->syncp);
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stats->tx_packets++;
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stats->tx_bytes += skb->len;
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u64_stats_update_end(&stats->syncp);
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return skb;
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}
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static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev,
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struct netdev_queue *netif_txq)
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{
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if (netif_tx_queue_stopped(netif_txq)) {
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/* Check whether the queue is stopped due to stalled
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* tx dma, if the queue is stopped then wake the queue
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* as we have free desc for tx
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*/
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__netif_tx_lock(netif_txq, smp_processor_id());
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if (netif_running(ndev) &&
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(k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS))
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netif_tx_wake_queue(netif_txq);
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__netif_tx_unlock(netif_txq);
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}
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}
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static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,
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int chn, unsigned int budget)
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{
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struct cppi5_host_desc_t *desc_tx;
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struct device *dev = common->dev;
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struct am65_cpsw_tx_chn *tx_chn;
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struct netdev_queue *netif_txq;
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@ -923,14 +970,55 @@ static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,
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struct sk_buff *skb;
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dma_addr_t desc_dma;
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int res, num_tx = 0;
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void **swdata;
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tx_chn = &common->tx_chns[chn];
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while (true) {
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struct am65_cpsw_ndev_priv *ndev_priv;
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struct am65_cpsw_ndev_stats *stats;
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spin_lock(&tx_chn->lock);
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res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
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spin_unlock(&tx_chn->lock);
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if (res == -ENODATA)
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break;
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if (cppi5_desc_is_tdcm(desc_dma)) {
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if (atomic_dec_and_test(&common->tdown_cnt))
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complete(&common->tdown_complete);
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break;
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}
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skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma);
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total_bytes = skb->len;
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ndev = skb->dev;
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napi_consume_skb(skb, budget);
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num_tx++;
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netif_txq = netdev_get_tx_queue(ndev, chn);
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netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
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am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
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}
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dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
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return num_tx;
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}
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static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common,
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int chn, unsigned int budget)
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{
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struct device *dev = common->dev;
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struct am65_cpsw_tx_chn *tx_chn;
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struct netdev_queue *netif_txq;
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unsigned int total_bytes = 0;
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struct net_device *ndev;
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struct sk_buff *skb;
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dma_addr_t desc_dma;
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int res, num_tx = 0;
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tx_chn = &common->tx_chns[chn];
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while (true) {
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res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
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if (res == -ENODATA)
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break;
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@ -941,23 +1029,9 @@ static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,
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break;
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}
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desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
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desc_dma);
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swdata = cppi5_hdesc_get_swdata(desc_tx);
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skb = *(swdata);
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am65_cpsw_nuss_xmit_free(tx_chn, dev, desc_tx);
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skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma);
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ndev = skb->dev;
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am65_cpts_tx_timestamp(common->cpts, skb);
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ndev_priv = netdev_priv(ndev);
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stats = this_cpu_ptr(ndev_priv->stats);
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u64_stats_update_begin(&stats->syncp);
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stats->tx_packets++;
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stats->tx_bytes += skb->len;
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u64_stats_update_end(&stats->syncp);
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total_bytes += skb->len;
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napi_consume_skb(skb, budget);
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num_tx++;
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@ -970,19 +1044,8 @@ static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,
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netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
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if (netif_tx_queue_stopped(netif_txq)) {
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/* Check whether the queue is stopped due to stalled tx dma,
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* if the queue is stopped then wake the queue as
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* we have free desc for tx
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*/
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__netif_tx_lock(netif_txq, smp_processor_id());
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if (netif_running(ndev) &&
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(k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
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MAX_SKB_FRAGS))
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netif_tx_wake_queue(netif_txq);
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am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
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__netif_tx_unlock(netif_txq);
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}
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dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
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return num_tx;
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@ -993,8 +1056,11 @@ static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget)
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struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx);
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int num_tx;
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num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id,
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budget);
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if (AM65_CPSW_IS_CPSW2G(tx_chn->common))
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num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget);
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else
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num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget);
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num_tx = min(num_tx, budget);
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if (num_tx < budget) {
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napi_complete(napi_tx);
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@ -1139,7 +1205,13 @@ done_tx:
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cppi5_hdesc_set_pktlen(first_desc, pkt_len);
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desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc);
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ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
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if (AM65_CPSW_IS_CPSW2G(common)) {
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ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
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} else {
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spin_lock_bh(&tx_chn->lock);
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ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
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spin_unlock_bh(&tx_chn->lock);
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}
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if (ret) {
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dev_err(dev, "can't push desc %d\n", ret);
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/* inform bql */
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@ -1470,6 +1542,7 @@ static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common)
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snprintf(tx_chn->tx_chn_name,
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sizeof(tx_chn->tx_chn_name), "tx%d", i);
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spin_lock_init(&tx_chn->lock);
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tx_chn->common = common;
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tx_chn->id = i;
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tx_chn->descs_num = max_desc_num;
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@ -60,6 +60,7 @@ struct am65_cpsw_tx_chn {
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struct am65_cpsw_common *common;
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struct k3_cppi_desc_pool *desc_pool;
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struct k3_udma_glue_tx_channel *tx_chn;
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spinlock_t lock; /* protect TX rings in multi-port mode */
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int irq;
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u32 id;
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u32 descs_num;
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