forked from Minki/linux
ath9k_hw: Fix a reset failure on AR9382 (2x2).
AR9382 needs to be configured for the correct chain mask before running AGC/TxIQ caliberation. Otherwise reset would fail. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -718,12 +718,19 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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int val;
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/*
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* 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
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* running AGC/TxIQ cals
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*/
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ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
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val = REG_READ(ah, AR_ENT_OTP);
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ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
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if (val & AR_ENT_OTP_CHAIN2_DISABLE)
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ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
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else
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/*
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* 0x7 = 0b111 , AR9003 needs to be configured for 3-chain
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* mode before running AGC/TxIQ cals
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*/
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ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
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/* Do Tx IQ Calibration */
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ar9003_hw_tx_iq_cal(ah);
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@ -1065,6 +1065,8 @@ enum {
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#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
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#define AR_INTR_PRIO_SYNC_MASK 0x40cc
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#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
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#define AR_ENT_OTP 0x40d8
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#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
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#define AR_RTC_9300_PLL_DIV 0x000003ff
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#define AR_RTC_9300_PLL_DIV_S 0
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