ARM development for 5.7:
- replace setup_irq() with request_irq() for ebsa110, footbridge, rpc - fix clang assembly error in kexec code - remove .fixup section in boot stub - decompressor / EFI cache flushing updates -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuNNh8scc2k/wOAE+9OeQG+StrGQFAl6GMjUACgkQ9OeQG+St rGTQmxAAmExCDLhR5jPwpTRQycOfWbNCZ7U0o0/hofah/R5u0a3vsqZTsZ0vqTjZ NRasyW7h825AFiwJz7FT2celYSiZCOSox/PyRWToRAyD/k75FbcRVIYIT7Fw0IQS E1dnGgq/rcEFWJJ0DlZQ//FL6dZ3PionEbhoo6dhWd3hWkqZOwG9P+HtP965KqOU NPZSpK67y0zTn5y+oBiSGKii+Zl907LUNv7AhtmPXJNm87X+GCg7tMLUKbcU2V2a QETrLzvehLS8XSHfVTRoh1pHYGvxOHbmKQitrfUFvWnwPHdButabDPsZm1GvubM3 7uiC06s2UH6nnwSDbmZ5VmD0IGViAgocW+iCRj094mWO6DlfqD+eDmfBO+ZhCfVH rpoP9ge9GNHGGl0FhDulRLWrfnV4X+vq3keT5Duy8QrLkLvbI3IRUEjKrMT7Y+uM RLEoJL7Ym4HuuU+I9HAXsDFU3OqagJipjHKDGexaNd92JEISx0JZd6+nY5jB9JDF 5W6nxY1rbBnLKBLawUM5RRbUEoV+L31B6uVLxEbsiiQZtGON7lKzNSf1iX2f8Yjb U4PHRzUglZs5EZLpvM4uDxGhftPA+XdEbAW40Thsd3x1wn5tVtTMsb8cq8eNptNx IQqDCpazeHUYaXocH/p7fhufjwrChzSzq6TJh3BbmEEuIs3BoDA= =ySzP -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm Pull ARM updates from Russell King: - replace setup_irq() with request_irq() for ebsa110, footbridge, rpc - fix clang assembly error in kexec code - remove .fixup section in boot stub - decompressor / EFI cache flushing updates * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 8966/1: rpc: replace setup_irq() by request_irq() ARM: 8965/2: footbridge: replace setup_irq() by request_irq() ARM: 8964/1: ebsa110: replace setup_irq() by request_irq() ARM: 8962/1: kexec: drop invalid assembly argument ARM: decompressor: switch to by-VA cache maintenance for v7 cores ARM: decompressor: prepare cache_clean_flush for doing by-VA maintenance ARM: decompressor: factor out routine to obtain the inflated image size ARM: 8959/1: Remove unused .fixup section in boot stub ARM: allow unwinder to unwind recursive functions
This commit is contained in:
Linus Torvalds
commit
a943353d17
@ -151,6 +151,25 @@
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.L_\@:
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.endm
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/*
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* The kernel build system appends the size of the
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* decompressed kernel at the end of the compressed data
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* in little-endian form.
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*/
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.macro get_inflated_image_size, res:req, tmp1:req, tmp2:req
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adr \res, .Linflated_image_size_offset
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ldr \tmp1, [\res]
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add \tmp1, \tmp1, \res @ address of inflated image size
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ldrb \res, [\tmp1] @ get_unaligned_le32
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ldrb \tmp2, [\tmp1, #1]
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orr \res, \res, \tmp2, lsl #8
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ldrb \tmp2, [\tmp1, #2]
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ldrb \tmp1, [\tmp1, #3]
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orr \res, \res, \tmp2, lsl #16
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orr \res, \res, \tmp1, lsl #24
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.endm
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.section ".start", "ax"
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/*
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* sort out different calling conventions
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@ -268,15 +287,15 @@ not_angel:
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*/
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mov r0, pc
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cmp r0, r4
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ldrcc r0, LC0+32
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ldrcc r0, LC0+28
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addcc r0, r0, pc
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cmpcc r4, r0
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orrcc r4, r4, #1 @ remember we skipped cache_on
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blcs cache_on
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restart: adr r0, LC0
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ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
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ldr sp, [r0, #28]
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ldmia r0, {r1, r2, r3, r6, r11, r12}
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ldr sp, [r0, #24]
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/*
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* We might be running at a different address. We need
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@ -284,20 +303,8 @@ restart: adr r0, LC0
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*/
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sub r0, r0, r1 @ calculate the delta offset
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add r6, r6, r0 @ _edata
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add r10, r10, r0 @ inflated kernel size location
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/*
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* The kernel build system appends the size of the
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* decompressed kernel at the end of the compressed data
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* in little-endian form.
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*/
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ldrb r9, [r10, #0]
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ldrb lr, [r10, #1]
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orr r9, r9, lr, lsl #8
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ldrb lr, [r10, #2]
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ldrb r10, [r10, #3]
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orr r9, r9, lr, lsl #16
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orr r9, r9, r10, lsl #24
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get_inflated_image_size r9, r10, lr
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#ifndef CONFIG_ZBOOT_ROM
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/* malloc space is above the relocated stack (64k max) */
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@ -521,11 +528,8 @@ dtb_check_done:
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/* Preserve offset to relocated code. */
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sub r6, r9, r6
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#ifndef CONFIG_ZBOOT_ROM
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/* cache_clean_flush may use the stack, so relocate it */
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add sp, sp, r6
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#endif
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mov r0, r9 @ start of relocated zImage
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add r1, sp, r6 @ end of relocated zImage
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bl cache_clean_flush
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badr r0, restart
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@ -622,6 +626,11 @@ not_relocated: mov r0, #0
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add r2, sp, #0x10000 @ 64k max
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mov r3, r7
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bl decompress_kernel
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get_inflated_image_size r1, r2, r3
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mov r0, r4 @ start of inflated image
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add r1, r1, r0 @ end of inflated image
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bl cache_clean_flush
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bl cache_off
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@ -652,13 +661,15 @@ LC0: .word LC0 @ r1
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.word __bss_start @ r2
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.word _end @ r3
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.word _edata @ r6
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.word input_data_end - 4 @ r10 (inflated size location)
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.word _got_start @ r11
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.word _got_end @ ip
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.word .L_user_stack_end @ sp
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.word _end - restart + 16384 + 1024*1024
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.size LC0, . - LC0
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.Linflated_image_size_offset:
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.long (input_data_end - 4) - .
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#ifdef CONFIG_ARCH_RPC
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.globl params
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params: ldr r0, =0x10000100 @ params_phys for RPC
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@ -667,6 +678,24 @@ params: ldr r0, =0x10000100 @ params_phys for RPC
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.align
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#endif
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/*
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* dcache_line_size - get the minimum D-cache line size from the CTR register
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* on ARMv7.
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*/
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.macro dcache_line_size, reg, tmp
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#ifdef CONFIG_CPU_V7M
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movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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ldr \tmp, [\tmp]
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#else
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mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
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#endif
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lsr \tmp, \tmp, #16
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and \tmp, \tmp, #0xf @ cache line size encoding
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mov \reg, #4 @ bytes per word
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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/*
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* Turn on the cache. We need to setup some page tables so that we
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* can have both the I and D caches on.
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@ -1159,8 +1188,6 @@ __armv7_mmu_cache_off:
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bic r0, r0, #0x000c
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#endif
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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mov r12, lr
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bl __armv7_mmu_cache_flush
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mov r0, #0
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
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@ -1168,11 +1195,14 @@ __armv7_mmu_cache_off:
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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mov pc, r12
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mov pc, lr
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/*
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* Clean and flush the cache to maintain consistency.
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*
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* On entry,
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* r0 = start address
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* r1 = end address (exclusive)
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* On exit,
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* r1, r2, r3, r9, r10, r11, r12 corrupted
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* This routine must preserve:
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@ -1181,6 +1211,7 @@ __armv7_mmu_cache_off:
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.align 5
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cache_clean_flush:
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mov r3, #16
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mov r11, r1
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b call_cache_fn
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__armv4_mpu_cache_flush:
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@ -1231,51 +1262,16 @@ __armv7_mmu_cache_flush:
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mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
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b iflush
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hierarchical:
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mcr p15, 0, r10, c7, c10, 5 @ DMB
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stmfd sp!, {r0-r7, r9-r11}
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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loop1:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop2:
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mov r9, r4 @ create working copy of max way size
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loop3:
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ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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THUMB( lsl r6, r7, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3
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subs r7, r7, #1 @ decrement the index
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bge loop2
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt loop1
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finished:
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ldmfd sp!, {r0-r7, r9-r11}
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mov r10, #0 @ switch back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dcache_line_size r1, r2 @ r1 := dcache min line size
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sub r2, r1, #1 @ r2 := line size mask
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bic r0, r0, r2 @ round down start to line size
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sub r11, r11, #1 @ end address is exclusive
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bic r11, r11, r2 @ round down end to line size
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0: cmp r0, r11 @ finished?
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bgt iflush
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mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
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add r0, r0, r1
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b 0b
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iflush:
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mcr p15, 0, r10, c7, c10, 4 @ DSB
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mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
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@ -36,7 +36,6 @@ SECTIONS
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*(.start)
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*(.text)
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*(.text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.glue_7t)
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*(.glue_7)
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@ -25,26 +25,26 @@ ENTRY(relocate_new_kernel)
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ldr r3, [r0],#4
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/* Is it a destination page. Put destination address to r4 */
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tst r3,#1,0
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tst r3,#1
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beq 1f
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bic r4,r3,#1
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b 0b
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1:
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/* Is it an indirection page */
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tst r3,#2,0
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tst r3,#2
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beq 1f
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bic r0,r3,#2
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b 0b
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1:
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/* are we done ? */
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tst r3,#4,0
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tst r3,#4
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beq 1f
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b 2f
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1:
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/* is it source ? */
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tst r3,#8,0
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tst r3,#8
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beq 0b
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bic r3,r3,#8
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mov r6,#1024
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@ -444,7 +444,7 @@ int unwind_frame(struct stackframe *frame)
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ctrl.vrs[PC] = ctrl.vrs[LR];
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/* check for infinite loop */
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if (frame->pc == ctrl.vrs[PC])
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if (frame->pc == ctrl.vrs[PC] && frame->sp == ctrl.vrs[SP])
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return -URC_FAILURE;
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frame->fp = ctrl.vrs[FP];
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@ -201,17 +201,13 @@ ebsa110_timer_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static struct irqaction ebsa110_timer_irq = {
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.name = "EBSA110 Timer Tick",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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||||
.handler = ebsa110_timer_interrupt,
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||||
};
|
||||
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||||
/*
|
||||
* Set up timer interrupt.
|
||||
*/
|
||||
void __init ebsa110_timer_init(void)
|
||||
{
|
||||
int irq = IRQ_EBSA110_TIMER0;
|
||||
|
||||
arch_gettimeoffset = ebsa110_gettimeoffset;
|
||||
|
||||
/*
|
||||
@ -221,7 +217,9 @@ void __init ebsa110_timer_init(void)
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__raw_writeb(COUNT & 0xff, PIT_T1);
|
||||
__raw_writeb(COUNT >> 8, PIT_T1);
|
||||
|
||||
setup_irq(IRQ_EBSA110_TIMER0, &ebsa110_timer_irq);
|
||||
if (request_irq(irq, ebsa110_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
|
||||
"EBSA110 Timer Tick", NULL))
|
||||
pr_err("Failed to request irq %d (EBSA110 Timer Tick)\n", irq);
|
||||
}
|
||||
|
||||
static struct plat_serial8250_port serial_platform_data[] = {
|
||||
|
||||
@ -101,13 +101,6 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction footbridge_timer_irq = {
|
||||
.name = "dc21285_timer1",
|
||||
.handler = timer1_interrupt,
|
||||
.flags = IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.dev_id = &ckevt_dc21285,
|
||||
};
|
||||
|
||||
/*
|
||||
* Set up timer interrupt.
|
||||
*/
|
||||
@ -118,7 +111,9 @@ void __init footbridge_timer_init(void)
|
||||
|
||||
clocksource_register_hz(&cksrc_dc21285, rate);
|
||||
|
||||
setup_irq(ce->irq, &footbridge_timer_irq);
|
||||
if (request_irq(ce->irq, timer1_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
|
||||
"dc21285_timer1", &ckevt_dc21285))
|
||||
pr_err("Failed to request irq %d (dc21285_timer1)", ce->irq);
|
||||
|
||||
ce->cpumask = cpumask_of(smp_processor_id());
|
||||
clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
|
||||
|
||||
@ -96,11 +96,6 @@ static void isa_irq_handler(struct irq_desc *desc)
|
||||
generic_handle_irq(isa_irq);
|
||||
}
|
||||
|
||||
static struct irqaction irq_cascade = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
};
|
||||
|
||||
static struct resource pic1_resource = {
|
||||
.name = "pic1",
|
||||
.start = 0x20,
|
||||
@ -160,7 +155,10 @@ void __init isa_init_irq(unsigned int host_irq)
|
||||
|
||||
request_resource(&ioport_resource, &pic1_resource);
|
||||
request_resource(&ioport_resource, &pic2_resource);
|
||||
setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
|
||||
|
||||
irq = IRQ_ISA_CASCADE;
|
||||
if (request_irq(irq, no_action, 0, "cascade", NULL))
|
||||
pr_err("Failed to request irq %u (cascade)\n", irq);
|
||||
|
||||
irq_set_chained_handler(host_irq, isa_irq_handler);
|
||||
|
||||
|
||||
@ -25,17 +25,12 @@ static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction pit_timer_irq = {
|
||||
.name = "pit",
|
||||
.handler = pit_timer_interrupt,
|
||||
.flags = IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.dev_id = &i8253_clockevent,
|
||||
};
|
||||
|
||||
void __init isa_timer_init(void)
|
||||
{
|
||||
clocksource_i8253_init();
|
||||
|
||||
setup_irq(i8253_clockevent.irq, &pit_timer_irq);
|
||||
if (request_irq(i8253_clockevent.irq, pit_timer_interrupt,
|
||||
IRQF_TIMER | IRQF_IRQPOLL, "pit", &i8253_clockevent))
|
||||
pr_err("Failed to request irq %d(pit)\n", i8253_clockevent.irq);
|
||||
clockevent_i8253_init(false);
|
||||
}
|
||||
|
||||
@ -85,11 +85,6 @@ ioc_timer_interrupt(int irq, void *dev_id)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction ioc_timer_irq = {
|
||||
.name = "timer",
|
||||
.handler = ioc_timer_interrupt
|
||||
};
|
||||
|
||||
/*
|
||||
* Set up timer interrupt.
|
||||
*/
|
||||
@ -97,5 +92,6 @@ void __init ioc_timer_init(void)
|
||||
{
|
||||
WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ));
|
||||
ioctime_init();
|
||||
setup_irq(IRQ_TIMER0, &ioc_timer_irq);
|
||||
if (request_irq(IRQ_TIMER0, ioc_timer_interrupt, 0, "timer", NULL))
|
||||
pr_err("Failed to request irq %d (timer)\n", IRQ_TIMER0);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user