forked from Minki/linux
iio:proximity:sx9324: Add dt_binding support
Based on bindings/iio/proximity/semtech,sx9324.yaml, implement retrieving sensor hardware property and alter default values. Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20220101203817.290512-6-gwendal@chromium.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Gwendal Grignou
Jonathan Cameron
parent
656f807086
commit
a8ee3b32f5
@ -77,6 +77,7 @@
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#define SX9324_REG_PROX_CTRL0 0x30
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#define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)
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#define SX9324_REG_PROX_CTRL0_GAIN_1 0x80
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#define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)
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#define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01
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#define SX9324_REG_PROX_CTRL1 0x31
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#define SX9324_REG_PROX_CTRL2 0x32
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@ -753,6 +754,74 @@ static int sx9324_write_raw(struct iio_dev *indio_dev,
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}
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}
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static const struct sx_common_reg_default sx9324_default_regs[] = {
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{ SX9324_REG_IRQ_MSK, 0x00 },
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{ SX9324_REG_IRQ_CFG0, 0x00 },
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{ SX9324_REG_IRQ_CFG1, SX9324_REG_IRQ_CFG1_FAILCOND },
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{ SX9324_REG_IRQ_CFG2, 0x00 },
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{ SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS },
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/*
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* The lower 4 bits should not be set as it enable sensors measurements.
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* Turning the detection on before the configuration values are set to
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* good values can cause the device to return erroneous readings.
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*/
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{ SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL },
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{ SX9324_REG_AFE_CTRL0, 0x00 },
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{ SX9324_REG_AFE_CTRL3, 0x00 },
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{ SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
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SX9324_REG_AFE_CTRL4_RES_100 },
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{ SX9324_REG_AFE_CTRL6, 0x00 },
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{ SX9324_REG_AFE_CTRL7, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
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SX9324_REG_AFE_CTRL4_RES_100 },
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/* TODO(gwendal): PHx use chip default or all grounded? */
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{ SX9324_REG_AFE_PH0, 0x29 },
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{ SX9324_REG_AFE_PH1, 0x26 },
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{ SX9324_REG_AFE_PH2, 0x1a },
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{ SX9324_REG_AFE_PH3, 0x16 },
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{ SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM },
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{ SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 },
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{ SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL0_GAIN_1 |
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SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
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{ SX9324_REG_PROX_CTRL1, SX9324_REG_PROX_CTRL0_GAIN_1 |
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SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
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{ SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K },
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{ SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES |
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SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K },
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{ SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 |
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SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 },
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{ SX9324_REG_PROX_CTRL5, 0x00 },
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{ SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 },
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{ SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 },
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{ SX9324_REG_ADV_CTRL0, 0x00 },
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{ SX9324_REG_ADV_CTRL1, 0x00 },
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{ SX9324_REG_ADV_CTRL2, 0x00 },
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{ SX9324_REG_ADV_CTRL3, 0x00 },
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{ SX9324_REG_ADV_CTRL4, 0x00 },
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{ SX9324_REG_ADV_CTRL5, SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 |
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SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 },
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{ SX9324_REG_ADV_CTRL6, 0x00 },
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{ SX9324_REG_ADV_CTRL7, 0x00 },
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{ SX9324_REG_ADV_CTRL8, 0x00 },
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{ SX9324_REG_ADV_CTRL9, 0x00 },
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/* Body/Table threshold */
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{ SX9324_REG_ADV_CTRL10, 0x00 },
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{ SX9324_REG_ADV_CTRL11, 0x00 },
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{ SX9324_REG_ADV_CTRL12, 0x00 },
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/* TODO(gwendal): SAR currenly disabled */
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{ SX9324_REG_ADV_CTRL13, 0x00 },
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{ SX9324_REG_ADV_CTRL14, 0x00 },
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{ SX9324_REG_ADV_CTRL15, 0x00 },
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{ SX9324_REG_ADV_CTRL16, 0x00 },
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{ SX9324_REG_ADV_CTRL17, 0x00 },
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{ SX9324_REG_ADV_CTRL18, 0x00 },
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{ SX9324_REG_ADV_CTRL19, SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION },
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{ SX9324_REG_ADV_CTRL20, SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION },
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};
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/* Activate all channels and perform an initial compensation. */
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static int sx9324_init_compensation(struct iio_dev *indio_dev)
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{
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@ -772,6 +841,99 @@ static int sx9324_init_compensation(struct iio_dev *indio_dev)
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20000, 2000000);
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}
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static const struct sx_common_reg_default *
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sx9324_get_default_reg(struct device *dev, int idx,
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struct sx_common_reg_default *reg_def)
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{
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#define SX9324_PIN_DEF "semtech,ph0-pin"
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#define SX9324_RESOLUTION_DEF "semtech,ph01-resolution"
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#define SX9324_PROXRAW_DEF "semtech,ph01-proxraw-strength"
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unsigned int pin_defs[SX9324_NUM_PINS];
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char prop[] = SX9324_PROXRAW_DEF;
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u32 start = 0, raw = 0, pos = 0;
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int ret, count, ph, pin;
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memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def));
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switch (reg_def->reg) {
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case SX9324_REG_AFE_PH0:
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case SX9324_REG_AFE_PH1:
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case SX9324_REG_AFE_PH2:
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case SX9324_REG_AFE_PH3:
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ph = reg_def->reg - SX9324_REG_AFE_PH0;
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scnprintf(prop, ARRAY_SIZE(prop), "semtech,ph%d-pin", ph);
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count = device_property_count_u32(dev, prop);
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if (count != ARRAY_SIZE(pin_defs))
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break;
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ret = device_property_read_u32_array(dev, prop, pin_defs,
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ARRAY_SIZE(pin_defs));
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for (pin = 0; pin < SX9324_NUM_PINS; pin++)
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raw |= (pin_defs[pin] << (2 * pin)) &
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SX9324_REG_AFE_PH0_PIN_MASK(pin);
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reg_def->def = raw;
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break;
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case SX9324_REG_AFE_CTRL4:
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case SX9324_REG_AFE_CTRL7:
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if (reg_def->reg == SX9324_REG_AFE_CTRL4)
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strncpy(prop, "semtech,ph01-resolution",
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ARRAY_SIZE(prop));
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else
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strncpy(prop, "semtech,ph23-resolution",
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ARRAY_SIZE(prop));
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ret = device_property_read_u32(dev, prop, &raw);
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if (ret)
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break;
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raw = ilog2(raw) - 3;
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reg_def->def &= ~SX9324_REG_AFE_CTRL4_RESOLUTION_MASK;
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reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK,
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raw);
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break;
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case SX9324_REG_ADV_CTRL5:
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ret = device_property_read_u32(dev, "semtech,startup-sensor",
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&start);
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if (ret)
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break;
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reg_def->def &= ~SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK;
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reg_def->def |= FIELD_PREP(SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK,
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start);
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break;
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case SX9324_REG_PROX_CTRL4:
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ret = device_property_read_u32(dev, "semtech,avg-pos-strength",
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&pos);
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if (ret)
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break;
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/* Powers of 2, except for a gap between 16 and 64 */
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raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3);
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reg_def->def &= ~SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK;
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reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK,
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raw);
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break;
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case SX9324_REG_PROX_CTRL0:
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case SX9324_REG_PROX_CTRL1:
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if (reg_def->reg == SX9324_REG_PROX_CTRL0)
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strncpy(prop, "semtech,ph01-proxraw-strength",
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ARRAY_SIZE(prop));
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else
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strncpy(prop, "semtech,ph23-proxraw-strength",
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ARRAY_SIZE(prop));
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ret = device_property_read_u32(dev, prop, &raw);
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if (ret)
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break;
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reg_def->def &= ~SX9324_REG_PROX_CTRL0_RAWFILT_MASK;
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reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL0_RAWFILT_MASK,
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raw);
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break;
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}
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return reg_def;
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}
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static int sx9324_check_whoami(struct device *dev,
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struct iio_dev *indio_dev)
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{
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@ -792,12 +954,14 @@ static const struct sx_common_chip_info sx9324_chip_info = {
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.mask_enable_chan = SX9324_REG_GNRL_CTRL1_PHEN_MASK,
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.irq_msk_offset = 3,
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.num_channels = SX9324_NUM_CHANNELS,
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.num_default_regs = ARRAY_SIZE(sx9324_default_regs),
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.ops = {
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.read_prox_data = sx9324_read_prox_data,
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.check_whoami = sx9324_check_whoami,
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.init_compensation = sx9324_init_compensation,
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.wait_for_sample = sx9324_wait_for_sample,
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.get_default_reg = sx9324_get_default_reg,
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},
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.iio_channels = sx9324_channels,
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