forked from Minki/linux
ASoC: davinci-mcasp: Add overrun/underrun event handling
An underrun (playback) event occurs when the serializer transfer data from the XRBUF buffer to the XRSR shift register, but the XRBUF hasn't been filled. Similarly, the overrun (capture) event occurs when data from the XRSR shift register is transferred to the XRBUF but it hasn't been read yet. These events are handled as XRUN events that cause the pcm to stop. The stream has to be explicitly restarted by the userspace which ensures that after stopping/starting McASP the data transfer is aligned with DMA. The other possibility was to internally stop and start McASP without DMA even knowing about it. Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Misael Lopez Cruz
Mark Brown
parent
18a4f55756
commit
a7a3324a60
@ -32,7 +32,7 @@ Optional properties:
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- rx-num-evt : FIFO levels.
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- sram-size-playback : size of sram to be allocated during playback
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- sram-size-capture : size of sram to be allocated during capture
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- interrupts : Interrupt numbers for McASP, currently not used by the driver
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- interrupts : Interrupt numbers for McASP
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- interrupt-names : Known interrupt names are "tx" and "rx"
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- pinctrl-0: Should specify pin control group used for this controller.
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- pinctrl-names: Should contain only one value - "default", for more details
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@ -70,6 +70,7 @@ struct davinci_mcasp {
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void __iomem *base;
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u32 fifo_base;
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struct device *dev;
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struct snd_pcm_substream *substreams[2];
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/* McASP specific data */
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int tdm_slots;
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@ -80,6 +81,7 @@ struct davinci_mcasp {
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u8 bclk_div;
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u16 bclk_lrclk_ratio;
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int streams;
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u32 irq_request[2];
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int sysclk_freq;
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bool bclk_master;
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@ -185,6 +187,10 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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if (mcasp_is_synchronous(mcasp))
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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/* enable receive IRQs */
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mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
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mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
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}
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static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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@ -214,6 +220,10 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
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/* Release Frame Sync generator */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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/* enable transmit IRQs */
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mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
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mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
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}
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static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
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@ -228,6 +238,10 @@ static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
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static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
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{
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/* disable IRQ sources */
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
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mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
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/*
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* In synchronous mode stop the TX clocks if no other stream is
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* running
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@ -249,6 +263,10 @@ static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
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{
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u32 val = 0;
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/* disable IRQ sources */
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
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mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
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/*
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* In synchronous mode keep TX clocks running if the capture stream is
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* still running.
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@ -276,6 +294,76 @@ static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
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mcasp_stop_rx(mcasp);
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}
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static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
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{
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struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
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struct snd_pcm_substream *substream;
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u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
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u32 handled_mask = 0;
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u32 stat;
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stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
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if (stat & XUNDRN & irq_mask) {
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dev_warn(mcasp->dev, "Transmit buffer underflow\n");
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handled_mask |= XUNDRN;
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substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
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if (substream) {
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snd_pcm_stream_lock_irq(substream);
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if (snd_pcm_running(substream))
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snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
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snd_pcm_stream_unlock_irq(substream);
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}
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}
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if (!handled_mask)
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dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
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stat);
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if (stat & XRERR)
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handled_mask |= XRERR;
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/* Ack the handled event only */
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
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return IRQ_RETVAL(handled_mask);
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}
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static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
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{
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struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
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struct snd_pcm_substream *substream;
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u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
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u32 handled_mask = 0;
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u32 stat;
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stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
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if (stat & ROVRN & irq_mask) {
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dev_warn(mcasp->dev, "Receive buffer overflow\n");
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handled_mask |= ROVRN;
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substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
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if (substream) {
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snd_pcm_stream_lock_irq(substream);
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if (snd_pcm_running(substream))
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snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
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snd_pcm_stream_unlock_irq(substream);
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}
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}
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if (!handled_mask)
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dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
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stat);
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if (stat & XRERR)
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handled_mask |= XRERR;
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/* Ack the handled event only */
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mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
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return IRQ_RETVAL(handled_mask);
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}
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static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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@ -869,6 +957,8 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
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u32 max_channels = 0;
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int i, dir;
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mcasp->substreams[substream->stream] = substream;
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if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
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return 0;
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@ -907,6 +997,8 @@ static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
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{
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struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
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mcasp->substreams[substream->stream] = NULL;
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if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
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return;
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@ -1256,6 +1348,8 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
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struct resource *mem, *ioarea, *res, *dat;
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struct davinci_mcasp_pdata *pdata;
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struct davinci_mcasp *mcasp;
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char *irq_name;
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int irq;
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int ret;
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if (!pdev->dev.platform_data && !pdev->dev.of_node) {
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@ -1336,6 +1430,36 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
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mcasp->dev = &pdev->dev;
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irq = platform_get_irq_byname(pdev, "rx");
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if (irq >= 0) {
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irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n",
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dev_name(&pdev->dev));
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ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
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davinci_mcasp_rx_irq_handler,
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IRQF_ONESHOT, irq_name, mcasp);
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if (ret) {
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dev_err(&pdev->dev, "RX IRQ request failed\n");
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goto err;
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}
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mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
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}
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irq = platform_get_irq_byname(pdev, "tx");
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if (irq >= 0) {
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irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n",
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dev_name(&pdev->dev));
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ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
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davinci_mcasp_tx_irq_handler,
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IRQF_ONESHOT, irq_name, mcasp);
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if (ret) {
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dev_err(&pdev->dev, "TX IRQ request failed\n");
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goto err;
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}
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mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
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}
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dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
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if (dat)
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mcasp->dat_port = true;
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@ -256,6 +256,7 @@
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* DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
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* DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
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*/
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#define XRERR BIT(8) /* Transmit/Receive error */
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#define XRDATA BIT(5) /* Transmit/Receive data ready */
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/*
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@ -284,6 +285,16 @@
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*/
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#define TXDATADMADIS BIT(0)
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/*
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* DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits
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*/
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#define ROVRN BIT(0)
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/*
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* DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits
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*/
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#define XUNDRN BIT(0)
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/*
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* DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
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*/
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