ASoC: SOF: Intel: hda-stream: limit PROCEN workaround
The work-around enabled in hda-stream.c is only required on earlier versions of SOCs/PCH (Skylake, KabyLake, ApolloLake, GeminiLake). Before setting the format on the host DMA, it is required to couple the host and link DMA - which as a consequence shall use the same format. This patch introduces a quirk field in the platform descriptor and makes the work-around conditional. Newer platforms have no limitations on the use of host and link DMA, which can use different formats. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Link: https://lore.kernel.org/r/20211207193947.71080-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -147,5 +147,6 @@ const struct sof_intel_dsp_desc apl_chip_info = {
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.rom_init_timeout = 150,
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.ssp_count = APL_SSP_COUNT,
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.ssp_base_offset = APL_SSP_BASE_OFFSET,
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.quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
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};
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EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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@ -472,6 +472,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
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struct snd_dma_buffer *dmab,
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struct snd_pcm_hw_params *params)
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{
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const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_stream *hstream = &stream->hstream;
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int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
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@ -584,6 +585,7 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
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/*
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* Recommended hardware programming sequence for HDAudio DMA format
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* on earlier platforms - this is not needed on newer platforms
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*
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* 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit
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* for corresponding stream index before the time of writing
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@ -593,9 +595,11 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
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* enable decoupled mode
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*/
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/* couple host and link DMA, disable DSP features */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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mask, 0);
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if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) {
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/* couple host and link DMA, disable DSP features */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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mask, 0);
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}
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/* program stream format */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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@ -603,9 +607,11 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
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SOF_HDA_ADSP_REG_CL_SD_FORMAT,
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0xffff, hstream->format_val);
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/* decouple host and link DMA, enable DSP features */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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mask, mask);
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if (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK) {
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/* decouple host and link DMA, enable DSP features */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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mask, mask);
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}
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/* program last valid index */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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@ -151,6 +151,9 @@
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#define PCI_PMCS 0x84
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#define PCI_PMCS_PS_MASK 0x3
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/* Intel quirks */
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#define SOF_INTEL_PROCEN_FMT_QUIRK BIT(0)
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/* DSP hardware descriptor */
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struct sof_intel_dsp_desc {
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int cores_num;
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@ -166,6 +169,7 @@ struct sof_intel_dsp_desc {
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int ssp_base_offset; /* base address of the SSPs */
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u32 sdw_shim_base;
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u32 sdw_alh_base;
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u32 quirks;
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bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
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};
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