clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
This fixes register assignment in the CLK_PCLK_SMMU_GSCL{1,2} clocks definition. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -3411,11 +3411,11 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
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/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
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GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
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/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
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GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
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ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
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};
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static struct samsung_cmu_info gscl_cmu_info __initdata = {
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