forked from Minki/linux
davinci: add CPU idle driver
The patch adds support for DaVinci cpu idle driver. Two idle states are defined: 1. Wait for interrupt 2. Wait for interrupt and DDR self-refresh (or power down) Some DaVinci SoCs support putting DDR in self-refresh (eg Dm644x, DM6467) while others support putting DDR in self-refresh and power down (eg DM35x, DA8xx). Putting DDR (or mDDR) in power down saves more power than self-refresh. The patch has been tested on DA850/OMAP-L138 EVM. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sekhar Nori
Kevin Hilman
parent
1ef203c324
commit
a6c0f6eca1
@ -32,3 +32,4 @@ obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
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# Power Management
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obj-$(CONFIG_CPU_FREQ) += cpufreq.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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197
arch/arm/mach-davinci/cpuidle.c
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197
arch/arm/mach-davinci/cpuidle.c
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@ -0,0 +1,197 @@
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/*
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* CPU idle for DaVinci SoCs
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*
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* Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
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*
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* Derived from Marvell Kirkwood CPU idle code
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* (arch/arm/mach-kirkwood/cpuidle.c)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/cpuidle.h>
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#include <linux/io.h>
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#include <asm/proc-fns.h>
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#include <mach/cpuidle.h>
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#define DAVINCI_CPUIDLE_MAX_STATES 2
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struct davinci_ops {
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void (*enter) (u32 flags);
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void (*exit) (u32 flags);
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u32 flags;
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};
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/* fields in davinci_ops.flags */
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#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
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static struct cpuidle_driver davinci_idle_driver = {
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.name = "cpuidle-davinci",
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.owner = THIS_MODULE,
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};
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static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
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static void __iomem *ddr2_reg_base;
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#define DDR2_SDRCR_OFFSET 0xc
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#define DDR2_SRPD_BIT BIT(23)
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#define DDR2_LPMODEN_BIT BIT(31)
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static void davinci_save_ddr_power(int enter, bool pdown)
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{
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u32 val;
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val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
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if (enter) {
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if (pdown)
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val |= DDR2_SRPD_BIT;
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else
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val &= ~DDR2_SRPD_BIT;
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val |= DDR2_LPMODEN_BIT;
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} else {
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val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
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}
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__raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
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}
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static void davinci_c2state_enter(u32 flags)
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{
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davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
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}
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static void davinci_c2state_exit(u32 flags)
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{
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davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
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}
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static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
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[1] = {
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.enter = davinci_c2state_enter,
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.exit = davinci_c2state_exit,
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},
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};
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/* Actual code that puts the SoC in different idle states */
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static int davinci_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_state *state)
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{
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struct davinci_ops *ops = cpuidle_get_statedata(state);
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struct timeval before, after;
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int idle_time;
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local_irq_disable();
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do_gettimeofday(&before);
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if (ops && ops->enter)
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ops->enter(ops->flags);
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/* Wait for interrupt state */
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cpu_do_idle();
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if (ops && ops->exit)
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ops->exit(ops->flags);
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do_gettimeofday(&after);
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local_irq_enable();
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idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
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(after.tv_usec - before.tv_usec);
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return idle_time;
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}
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static int __init davinci_cpuidle_probe(struct platform_device *pdev)
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{
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int ret;
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struct cpuidle_device *device;
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struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
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struct resource *ddr2_regs;
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resource_size_t len;
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device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
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if (!pdata) {
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dev_err(&pdev->dev, "cannot get platform data\n");
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return -ENOENT;
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}
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ddr2_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!ddr2_regs) {
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dev_err(&pdev->dev, "cannot get DDR2 controller register base");
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return -ENODEV;
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}
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len = resource_size(ddr2_regs);
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ddr2_regs = request_mem_region(ddr2_regs->start, len, ddr2_regs->name);
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if (!ddr2_regs)
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return -EBUSY;
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ddr2_reg_base = ioremap(ddr2_regs->start, len);
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if (!ddr2_reg_base) {
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ret = -ENOMEM;
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goto ioremap_fail;
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}
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ret = cpuidle_register_driver(&davinci_idle_driver);
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if (ret) {
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dev_err(&pdev->dev, "failed to register driver\n");
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goto driver_register_fail;
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}
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/* Wait for interrupt state */
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device->states[0].enter = davinci_enter_idle;
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device->states[0].exit_latency = 1;
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device->states[0].target_residency = 10000;
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device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
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strcpy(device->states[0].name, "WFI");
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strcpy(device->states[0].desc, "Wait for interrupt");
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/* Wait for interrupt and DDR self refresh state */
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device->states[1].enter = davinci_enter_idle;
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device->states[1].exit_latency = 10;
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device->states[1].target_residency = 10000;
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device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
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strcpy(device->states[1].name, "DDR SR");
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strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
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if (pdata->ddr2_pdown)
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davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
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cpuidle_set_statedata(&device->states[1], &davinci_states[1]);
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device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
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ret = cpuidle_register_device(device);
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if (ret) {
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dev_err(&pdev->dev, "failed to register device\n");
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goto device_register_fail;
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}
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return 0;
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device_register_fail:
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cpuidle_unregister_driver(&davinci_idle_driver);
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driver_register_fail:
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iounmap(ddr2_reg_base);
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ioremap_fail:
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release_mem_region(ddr2_regs->start, len);
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return ret;
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}
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static struct platform_driver davinci_cpuidle_driver = {
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.driver = {
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.name = "cpuidle-davinci",
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.owner = THIS_MODULE,
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},
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};
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static int __init davinci_cpuidle_init(void)
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{
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return platform_driver_probe(&davinci_cpuidle_driver,
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davinci_cpuidle_probe);
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}
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device_initcall(davinci_cpuidle_init);
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17
arch/arm/mach-davinci/include/mach/cpuidle.h
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17
arch/arm/mach-davinci/include/mach/cpuidle.h
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@ -0,0 +1,17 @@
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/*
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* TI DaVinci cpuidle platform support
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*
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* 2009 (C) Texas Instruments, Inc. http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef _MACH_DAVINCI_CPUIDLE_H
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#define _MACH_DAVINCI_CPUIDLE_H
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struct davinci_cpuidle_config {
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u32 ddr2_pdown;
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};
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#endif
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