forked from Minki/linux
imx-drm: cleanups and YUV 4:2:0 memory read/write reduction support
- Remove counter load enable form PRE, which has no effect. - Add support for setting the double read/write reduction flag in channel parameter memory. This can be used to save some memory bandwidth when capturing in YUV 4:2:0 chroma subsampled formats. - Allocate DMA channel structures as needed, most of the 64 channels are unused or even reserved. - Remove unused interrupt busy waiting routine. - Set VDIC field order for both AUTO and MAN inputs simultaneously as both can't be active at the same time. -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEBsBxhV1FaKwXuCOBUMKIHHCeYOsFAlk49zAXHHAuemFiZWxA cGVuZ3V0cm9uaXguZGUACgkQUMKIHHCeYOtX+g/+M5DPkGhcP8fN9m47MOAEa+nP oDciYC76VrQev/Qys/zLM3/6sWF9h82USJ52H+zw41RuKKkYlcOzVWnSPQd2yN6Y hIl0fCsFzGxOMnIAhmi6BHFnvJKP1jsfeBdXSHyxI0y5kGoufG7BEHiJ7TTSgy/I JhccDKTRV9NzAfwpD37EI3a/Nc53DRpw3jrnHPnAaBJ6hYVPZ9YCSrBYbQQbIrDr x6NB8E1Ga3KRGZMTw45bTBiOs4AbZKSunzrqWQFnTRjbE+aTDs9W5n5wcdr7AoWi gqnx+b6TkiarNK3taHffjYioYvvn2nbGhuoAtg7hpS0CeUup0gitQquKM0kqsWnk yBykkP+Z7udASRgXdK6Gtzo6hzdhPeFPmmMbKmSBdIvT26t0ikf9RN1UlEhE6nY3 A68jKC4+gNTu8kF6imzWCfwM9KB4pWn0N0qTY5U9Y7/gWFky6IEDn3V5OM3XXqUa c/iglYyzO+B7vVu6ZajlH+shemO1mVaxGjVFrfX29syVooZrmo0NVJPdoKwiYx0r E08FCOdUIEhzFS6h1/FII+mZ6YzAmNkXVz+l+MWaoOW2tIWWX4xSsFTKBka2hDfq daU3CDcKcg8LuSybHg6lzj8Hw+/CWkqgtv6ESVnvHEUYCHoZsvArJTNoQrx/zJbE EwgZIM4daufEuv6I5zo= =m3BY -----END PGP SIGNATURE----- Merge tag 'imx-drm-next-2017-06-08' of git://git.pengutronix.de/git/pza/linux into drm-next imx-drm: cleanups and YUV 4:2:0 memory read/write reduction support - Remove counter load enable form PRE, which has no effect. - Add support for setting the double read/write reduction flag in channel parameter memory. This can be used to save some memory bandwidth when capturing in YUV 4:2:0 chroma subsampled formats. - Allocate DMA channel structures as needed, most of the 64 channels are unused or even reserved. - Remove unused interrupt busy waiting routine. - Set VDIC field order for both AUTO and MAN inputs simultaneously as both can't be active at the same time. * tag 'imx-drm-next-2017-06-08' of git://git.pengutronix.de/git/pza/linux: gpu: ipu-v3: vdic: include AUTO field order bit in ipu_vdi_set_field_order gpu: ipu-v3: remove interrupt busy waiting routine gpu: ipu-v3: allocate ipuv3_channels as needed gpu: ipu-v3: Add support for double read/write reduction gpu: ipu-v3: prg: remove counter load enable
This commit is contained in:
Dave Airlie
commit
a682169891
@ -274,15 +274,22 @@ struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
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mutex_lock(&ipu->channel_lock);
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channel = &ipu->channel[num];
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list_for_each_entry(channel, &ipu->channels, list) {
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if (channel->num == num) {
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channel = ERR_PTR(-EBUSY);
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goto out;
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}
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}
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if (channel->busy) {
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channel = ERR_PTR(-EBUSY);
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channel = kzalloc(sizeof(*channel), GFP_KERNEL);
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if (!channel) {
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channel = ERR_PTR(-ENOMEM);
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goto out;
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}
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channel->busy = true;
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channel->num = num;
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channel->ipu = ipu;
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list_add(&channel->list, &ipu->channels);
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out:
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mutex_unlock(&ipu->channel_lock);
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@ -299,7 +306,8 @@ void ipu_idmac_put(struct ipuv3_channel *channel)
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mutex_lock(&ipu->channel_lock);
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channel->busy = false;
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list_del(&channel->list);
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kfree(channel);
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mutex_unlock(&ipu->channel_lock);
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}
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@ -589,22 +597,6 @@ int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
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int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
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{
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(ms);
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ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
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while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cpu_relax();
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
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int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
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{
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struct ipu_soc *ipu = channel->ipu;
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@ -1376,7 +1368,7 @@ static int ipu_probe(struct platform_device *pdev)
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struct ipu_soc *ipu;
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struct resource *res;
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unsigned long ipu_base;
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int i, ret, irq_sync, irq_err;
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int ret, irq_sync, irq_err;
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const struct ipu_devtype *devtype;
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devtype = of_device_get_match_data(&pdev->dev);
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@ -1409,13 +1401,12 @@ static int ipu_probe(struct platform_device *pdev)
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return -EPROBE_DEFER;
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}
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for (i = 0; i < 64; i++)
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ipu->channel[i].ipu = ipu;
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ipu->devtype = devtype;
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ipu->ipu_type = devtype->type;
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spin_lock_init(&ipu->lock);
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mutex_init(&ipu->channel_lock);
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INIT_LIST_HEAD(&ipu->channels);
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dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
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ipu_base + devtype->cm_ofs);
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@ -224,6 +224,12 @@ void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);
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void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch)
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{
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ipu_ch_param_write_field(ch, IPU_FIELD_RDRW, 1);
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_skip_odd_chroma_rows);
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void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
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{
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ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
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@ -318,8 +318,6 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
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writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
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val = readl(prg->regs + IPU_PRG_CTL);
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/* counter load enable */
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val |= IPU_PRG_CTL_CNT_LOAD_EN(prg_chan);
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/* config AXI ID */
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val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
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IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));
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@ -157,11 +157,8 @@ enum ipu_modules {
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struct ipuv3_channel {
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unsigned int num;
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bool enabled;
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bool busy;
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struct ipu_soc *ipu;
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struct list_head list;
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};
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struct ipu_cpmem;
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@ -184,6 +181,7 @@ struct ipu_soc {
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enum ipuv3_type ipu_type;
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spinlock_t lock;
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struct mutex channel_lock;
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struct list_head channels;
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void __iomem *cm_reg;
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void __iomem *idmac_reg;
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@ -193,8 +191,6 @@ struct ipu_soc {
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struct clk *clk;
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struct ipuv3_channel channel[64];
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int irq_sync;
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int irq_err;
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struct irq_domain *domain;
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@ -229,7 +225,6 @@ int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
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int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
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bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
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int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms);
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int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
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unsigned long base, u32 module, struct clk *clk_ipu);
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@ -88,9 +88,9 @@ void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field)
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reg = ipu_vdi_read(vdi, VDI_C);
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if (top_field_0)
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reg &= ~VDI_C_TOP_FIELD_MAN_1;
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reg &= ~(VDI_C_TOP_FIELD_MAN_1 | VDI_C_TOP_FIELD_AUTO_1);
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else
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reg |= VDI_C_TOP_FIELD_MAN_1;
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reg |= VDI_C_TOP_FIELD_MAN_1 | VDI_C_TOP_FIELD_AUTO_1;
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ipu_vdi_write(vdi, reg, VDI_C);
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spin_unlock_irqrestore(&vdi->lock, flags);
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@ -250,6 +250,7 @@ struct ipu_image {
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void ipu_cpmem_zero(struct ipuv3_channel *ch);
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void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
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void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
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void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
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void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
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void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
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