drm/i915/ddi: Don't rewrite DDI_BUF_CTL reg during DP link training
The value we program to DDI_BUF_CTL changes at the following places: - At enabling/disabling the output to configure the port width etc, and to enable/disable the DDI BUF function. - At the beginning/end of link re-training to disable/re-enable the DDI BUF function. - On HSW/BDW/SKL to change the voltage swing/pre-emph levels. Except of the above the value we program to the DDI_BUF_CTL register (intel_dp->DP) doesn't change, so no need to reprogram the register when changing the link training patterns (which is programmed via the DP_TP_CTL register on DDI platforms). v2: - Fix the commit message wrt. voltage/pre-emph level values in intel_dp->DP. (Ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200714153141.10280-2-imre.deak@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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@ -4060,7 +4060,6 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
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enum port port = dp_to_dig_port(intel_dp)->base.port;
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u32 temp;
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temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
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@ -4085,9 +4084,6 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
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}
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intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
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intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
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intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
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}
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static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
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