dt-bindings: serial: qcom,msm-uartdm: convert to dtschema
Convert the Qualcomm MSM Serial UARTDM bindings to DT Schema. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220405063451.12011-8-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski
Rob Herring
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* MSM Serial UARTDM
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The MSM serial UARTDM hardware is designed for high-speed use cases where the
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transmit and/or receive channels can be offloaded to a dma-engine. From a
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software perspective it's mostly compatible with the MSM serial UART except
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that it supports reading and writing multiple characters at a time.
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Required properties:
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- compatible: Should contain at least "qcom,msm-uartdm".
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A more specific property should be specified as follows depending
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on the version:
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"qcom,msm-uartdm-v1.1"
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"qcom,msm-uartdm-v1.2"
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"qcom,msm-uartdm-v1.3"
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"qcom,msm-uartdm-v1.4"
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- reg: Should contain UART register locations and lengths. The first
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register shall specify the main control registers. An optional second
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register location shall specify the GSBI control region.
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"qcom,msm-uartdm-v1.3" is the only compatible value that might
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need the GSBI control region.
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- interrupts: Should contain UART interrupt.
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- clocks: Should contain the core clock and the AHB clock.
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- clock-names: Should be "core" for the core clock and "iface" for the
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AHB clock.
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Optional properties:
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- dmas: Should contain dma specifiers for transmit and receive channels
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- dma-names: Should contain "tx" for transmit and "rx" for receive channels
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- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be
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used with TX DMA channel. Required when using DMA for transmission
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with UARTDM v1.3 and below.
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- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be
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used with RX DMA channel. Required when using DMA for reception
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with UARTDM v1.3 and below.
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Note: Aliases may be defined to ensure the correct ordering of the UARTs.
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The alias serialN will result in the UART being assigned port N. If any
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serialN alias exists, then an alias must exist for each enabled UART. The
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serialN aliases should be in a .dts file instead of in a .dtsi file.
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Examples:
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- A uartdm v1.4 device with dma capabilities.
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serial@f991e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991e000 0x1000>;
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interrupts = <0 108 0x0>;
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clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
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clock-names = "core", "iface";
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dmas = <&dma0 0>, <&dma0 1>;
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dma-names = "tx", "rx";
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};
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- A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
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serial@19c40000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x19c40000 0x1000>,
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<0x19c00000 0x1000>;
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interrupts = <0 195 0x0>;
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clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
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clock-names = "core", "iface";
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};
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- serialN alias.
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aliases {
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serial0 = &uarta;
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serial1 = &uartc;
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serial2 = &uartb;
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};
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uarta: serial@12490000 {
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};
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uartb: serial@16340000 {
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};
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uartc: serial@1a240000 {
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};
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112
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml
Normal file
112
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml
Normal file
@ -0,0 +1,112 @@
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm MSM Serial UARTDM
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description: |
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The MSM serial UARTDM hardware is designed for high-speed use cases where the
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transmit and/or receive channels can be offloaded to a dma-engine. From a
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software perspective it's mostly compatible with the MSM serial UART except
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that it supports reading and writing multiple characters at a time.
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Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
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The alias serialN will result in the UART being assigned port N. If any
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serialN alias exists, then an alias must exist for each enabled UART. The
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serialN aliases should be in a .dts file instead of in a .dtsi file.
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properties:
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compatible:
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items:
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- enum:
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- qcom,msm-uartdm-v1.1
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- qcom,msm-uartdm-v1.2
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- qcom,msm-uartdm-v1.3
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- qcom,msm-uartdm-v1.4
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- const: qcom,msm-uartdm
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: iface
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interrupts:
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maxItems: 1
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qcom,rx-crci:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Identificator for Client Rate Control Interface to be used with RX DMA
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channel. Required when using DMA for reception with UARTDM v1.3 and
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below.
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qcom,tx-crci:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Identificator for Client Rate Control Interface to be used with TX DMA
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channel. Required when using DMA for transmission with UARTDM v1.3 and
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below.
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reg:
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minItems: 1
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items:
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- description: Main control registers
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- description: An optional second register location shall specify the GSBI control region.
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required:
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- compatible
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- clock-names
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- clocks
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- interrupts
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- reg
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unevaluatedProperties: false
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allOf:
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- $ref: /schemas/serial/serial.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: qcom,msm-uartdm-v1.3
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then:
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properties:
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reg:
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minItems: 2
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else:
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properties:
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reg:
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maxItems: 1
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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serial@f991e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991e000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
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clock-names = "core", "iface";
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dmas = <&dma0 0>, <&dma0 1>;
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dma-names = "tx", "rx";
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};
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