leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: mvebu: conditionalize Armada 375 SMP workaround

Browse Source 
The Armada 375 SMP workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.

Note that the initialization of the SMP workaround is delayed from
->smp_prepare_cpus() to ->smp_boot_secondary() because when
->smp_prepare_cpus() is called, the early initcalls have not be
called, so the mvebu-soc-id mechanism is not operational. Since the
workaround is anyway not needed before the secondary CPU is started,
we can delay its implementation until the ->smp_boot_secondary() call.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Thomas Petazzoni 2014-05-05 17:05:25 +02:00 committed by Jason Cooper
parent 5093dcfb42
commit a58d5af7d9
1 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm/mach-mvebu/platsmp-a9.c
View File

@ -20,6 +20,7 @@
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
#include "common.h" #include "common.h"
#include "mvebu-soc-id.h"
#include "pmsu.h" #include "pmsu.h"
#define CRYPT0_ENG_ID 41 #define CRYPT0_ENG_ID 41
@ -63,11 +64,19 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
*/ */
hw_cpu = cpu_logical_map(cpu); hw_cpu = cpu_logical_map(cpu);
if (of_machine_is_compatible("marvell,armada375")) if (of_machine_is_compatible("marvell,armada375")) {
u32 dev, rev;
if (mvebu_get_soc_id(&dev, &rev) == 0 &&
rev == ARMADA_375_Z1_REV)
armada_375_smp_cpu1_enable_wa();
mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup); mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup);
else }
else {
mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_pmsu_set_cpu_boot_addr(hw_cpu,
mvebu_cortex_a9_secondary_startup); mvebu_cortex_a9_secondary_startup);
}
smp_wmb(); smp_wmb();
ret = mvebu_cpu_reset_deassert(hw_cpu); ret = mvebu_cpu_reset_deassert(hw_cpu);
@ -80,14 +89,7 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
return 0; return 0;
} }
static void __init mvebu_cortex_a9_smp_prepare_cpus(unsigned int max_cpus)
{
if (of_machine_is_compatible("marvell,armada375"))
armada_375_smp_cpu1_enable_wa();
}
static struct smp_operations mvebu_cortex_a9_smp_ops __initdata = { static struct smp_operations mvebu_cortex_a9_smp_ops __initdata = {
.smp_prepare_cpus = mvebu_cortex_a9_smp_prepare_cpus,
.smp_boot_secondary = mvebu_cortex_a9_boot_secondary, .smp_boot_secondary = mvebu_cortex_a9_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU #ifdef CONFIG_HOTPLUG_CPU
.cpu_die = armada_xp_cpu_die, .cpu_die = armada_xp_cpu_die,