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[media] mt9m032: Fix PLL setup

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The MT9M032 PLL was assumed to be identical to the MT9P031 PLL but
differs significantly. Update the registers definitions and PLL limits
according to the datasheet.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Laurent Pinchart 2012-09-25 10:46:34 -03:00 committed by Mauro Carvalho Chehab
parent b54373c549
commit a54b80b17a
1 changed files with 13 additions and 11 deletions
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24
drivers/media/i2c/mt9m032.c
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@ -87,7 +87,7 @@
#define MT9M032_RESTART 0x0b #define MT9M032_RESTART 0x0b
#define MT9M032_RESET 0x0d #define MT9M032_RESET 0x0d
#define MT9M032_PLL_CONFIG1 0x11 #define MT9M032_PLL_CONFIG1 0x11
#define MT9M032_PLL_CONFIG1_OUTDIV_MASK 0x3f #define MT9M032_PLL_CONFIG1_PREDIV_MASK 0x3f
#define MT9M032_PLL_CONFIG1_MUL_SHIFT 8 #define MT9M032_PLL_CONFIG1_MUL_SHIFT 8
#define MT9M032_READ_MODE1 0x1e #define MT9M032_READ_MODE1 0x1e
#define MT9M032_READ_MODE2 0x20 #define MT9M032_READ_MODE2 0x20
@ -106,6 +106,8 @@
#define MT9M032_GAIN_AMUL_SHIFT 6 #define MT9M032_GAIN_AMUL_SHIFT 6
#define MT9M032_GAIN_ANALOG_MASK 0x3f #define MT9M032_GAIN_ANALOG_MASK 0x3f
#define MT9M032_FORMATTER1 0x9e #define MT9M032_FORMATTER1 0x9e
#define MT9M032_FORMATTER1_PLL_P1_6 (1 << 8)
#define MT9M032_FORMATTER1_PARALLEL (1 << 12)
#define MT9M032_FORMATTER2 0x9f #define MT9M032_FORMATTER2 0x9f
#define MT9M032_FORMATTER2_DOUT_EN 0x1000 #define MT9M032_FORMATTER2_DOUT_EN 0x1000
#define MT9M032_FORMATTER2_PIXCLK_EN 0x2000 #define MT9M032_FORMATTER2_PIXCLK_EN 0x2000
@ -121,8 +123,6 @@
#define MT9P031_PLL_CONTROL_PWROFF 0x0050 #define MT9P031_PLL_CONTROL_PWROFF 0x0050
#define MT9P031_PLL_CONTROL_PWRON 0x0051 #define MT9P031_PLL_CONTROL_PWRON 0x0051
#define MT9P031_PLL_CONTROL_USEPLL 0x0052 #define MT9P031_PLL_CONTROL_USEPLL 0x0052
#define MT9P031_PLL_CONFIG2 0x11
#define MT9P031_PLL_CONFIG2_P1_DIV_MASK 0x1f
struct mt9m032 { struct mt9m032 {
struct v4l2_subdev subdev; struct v4l2_subdev subdev;
@ -255,13 +255,14 @@ static int mt9m032_setup_pll(struct mt9m032 *sensor)
.n_max = 64, .n_max = 64,
.m_min = 16, .m_min = 16,
.m_max = 255, .m_max = 255,
.p1_min = 1, .p1_min = 6,
.p1_max = 128, .p1_max = 7,
}; };
struct i2c_client *client = v4l2_get_subdevdata(&sensor->subdev); struct i2c_client *client = v4l2_get_subdevdata(&sensor->subdev);
struct mt9m032_platform_data *pdata = sensor->pdata; struct mt9m032_platform_data *pdata = sensor->pdata;
struct aptina_pll pll; struct aptina_pll pll;
u16 reg_val;
int ret; int ret;
pll.ext_clock = pdata->ext_clock; pll.ext_clock = pdata->ext_clock;
@ -274,18 +275,19 @@ static int mt9m032_setup_pll(struct mt9m032 *sensor)
sensor->pix_clock = pdata->pix_clock; sensor->pix_clock = pdata->pix_clock;
ret = mt9m032_write(client, MT9M032_PLL_CONFIG1, ret = mt9m032_write(client, MT9M032_PLL_CONFIG1,
(pll.m << MT9M032_PLL_CONFIG1_MUL_SHIFT) (pll.m << MT9M032_PLL_CONFIG1_MUL_SHIFT) |
| (pll.p1 - 1)); ((pll.n - 1) & MT9M032_PLL_CONFIG1_PREDIV_MASK));
if (!ret)
ret = mt9m032_write(client, MT9P031_PLL_CONFIG2, pll.n - 1);
if (!ret) if (!ret)
ret = mt9m032_write(client, MT9P031_PLL_CONTROL, ret = mt9m032_write(client, MT9P031_PLL_CONTROL,
MT9P031_PLL_CONTROL_PWRON | MT9P031_PLL_CONTROL_PWRON |
MT9P031_PLL_CONTROL_USEPLL); MT9P031_PLL_CONTROL_USEPLL);
if (!ret) /* more reserved, Continuous, Master Mode */ if (!ret) /* more reserved, Continuous, Master Mode */
ret = mt9m032_write(client, MT9M032_READ_MODE1, 0x8006); ret = mt9m032_write(client, MT9M032_READ_MODE1, 0x8006);
if (!ret) /* Set 14-bit mode, select 7 divider */ if (!ret) {
ret = mt9m032_write(client, MT9M032_FORMATTER1, 0x111e); reg_val = (pll.p1 == 6 ? MT9M032_FORMATTER1_PLL_P1_6 : 0)
| MT9M032_FORMATTER1_PARALLEL | 0x001e; /* 14-bit */
ret = mt9m032_write(client, MT9M032_FORMATTER1, reg_val);
}
return ret; return ret;
} }