drm/amd/display: Only flush delta from last command execution
[Why] We're currently flushing commands that had been previously been flushed or are currently being processed by the DMCUB when we don't immediately wait for idle after command execution. [How] Avoiding reflushing the data by keeping track of the last wptr. We'll treat this as the actual rptr by creating a copy of the inbox and modifying the copy's rptr. Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -411,6 +411,7 @@ struct dmub_srv {
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struct dmub_srv_base_funcs funcs;
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struct dmub_srv_hw_funcs hw_funcs;
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struct dmub_rb inbox1_rb;
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uint32_t inbox1_last_wptr;
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/**
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* outbox1_rb is accessed without locks (dal & dc)
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* and to be used only in dmub_srv_stat_get_notification()
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@ -609,6 +609,8 @@ enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
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enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
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{
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struct dmub_rb flush_rb;
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if (!dmub->hw_init)
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return DMUB_STATUS_INVALID;
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@ -617,9 +619,14 @@ enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
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* been flushed to framebuffer memory. Otherwise DMCUB might
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* read back stale, fully invalid or partially invalid data.
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*/
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dmub_rb_flush_pending(&dmub->inbox1_rb);
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flush_rb = dmub->inbox1_rb;
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flush_rb.rptr = dmub->inbox1_last_wptr;
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dmub_rb_flush_pending(&flush_rb);
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dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
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dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
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return DMUB_STATUS_OK;
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}
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